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AJvYcCUSeaYCtEudQRktxWIXhVNtmJKFveQ0u7rzS/k8rVGTbM9BNdJ8xStwPCHmnQ69fymK0rgk6T7nJRF2gw1IiHymQq3Z8Kb9bmvBefEbKA2+QBESUl9Ssvig4I/VsRrz13J8EQHpKUU+rQ== X-Gm-Message-State: AOJu0YzOyARoDEwBjI7CXgslZ5rFwbLLacXS1I5tvtIjVvJUXK17YrE/ CW8U0FIKKePOE5gmsZtZVFAloVU3Or7vp4zwvt/uKj25dU9IyR5+ X-Google-Smtp-Source: AGHT+IE9h/j9vRasi1T0pYNNw6BUnEyofz6Ipy5tbNh06AY/1L9BiplAs+KDU/GhOTCtDBzGYCYkzg== X-Received: by 2002:a05:600c:4f4b:b0:426:64a2:5375 with SMTP id 5b1f17b1804b1-42811d80105mr74380815e9.1.1722342380256; Tue, 30 Jul 2024 05:26:20 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:a2b2:16cc:b7df:405d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42813a5b3f6sm125366615e9.2.2024.07.30.05.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jul 2024 05:26:19 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Marc Zyngier , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 1/4] arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes Date: Tue, 30 Jul 2024 13:24:33 +0100 Message-Id: <20240730122436.350013-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730122436.350013-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240730122436.350013-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64kB + 64kB for the MBI alias (in total 128kB), and the GICR is 128kB per CPU. Despite the RZ/G3S SoC being single-core, it has two instances of GICR. Fixes: e20396d65b959 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC") Signed-off-by: Lad Prabhakar --- v1->v2 - Updated commit message --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0d5c47a65e46..34e29463a672 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -269,8 +269,8 @@ gic: interrupt-controller@12400000 { #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x12400000 0 0x40000>, - <0x0 0x12440000 0 0x60000>; + reg = <0x0 0x12400000 0 0x20000>, + <0x0 0x12440000 0 0x40000>; interrupts = ; };