| Message ID | 20240811204955.270231-8-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform | expand |
Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar <prabhakar.csengg@gmail.com> > Sent: Sunday, August 11, 2024 9:50 PM > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2 > connector) on the RZ/V2H GP-EVK platform. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > - New patch > --- > .../boot/dts/renesas/r9a09g057h44-gp-evk.dts | 191 ++++++++++++++++++ > 1 file changed, 191 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > index 593c48181248..11c13c85d278 100644 > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > @@ -7,6 +7,8 @@ > > /dts-v1/; > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > +#include <dt-bindings/gpio/gpio.h> > #include "r9a09g057.dtsi" > > / { > @@ -14,6 +16,14 @@ / { > compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; > > aliases { > + i2c0 = &i2c0; > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c6 = &i2c6; > + i2c7 = &i2c7; > + i2c8 = &i2c8; > + mmc1 = &sdhi1; > serial0 = &scif; > }; > > @@ -32,17 +42,186 @@ memory@240000000 { > device_type = "memory"; > reg = <0x2 0x40000000 0x2 0x00000000>; > }; > + > + reg_3p3v: regulator1 { > + compatible = "regulator-fixed"; > + > + regulator-name = "fixed-3.3V"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > + vqmmc_sdhi1: regulator-vccq-sdhi1 { > + compatible = "regulator-gpio"; > + regulator-name = "SDHI1 VccQ"; > + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + gpios-states = <0>; > + states = <3300000 0>, <1800000 1>; > + }; > }; > > &audio_extal_clk { > clock-frequency = <22579200>; > }; > > +&i2c0 { > + pinctrl-0 = <&i2c0_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + clock-frequency = <100000>; in SoC dtsim Why frequency set to 100kHz for all the i2c nodes even though SoC supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz? Cheers, Biju > +&i2c1 { > + pinctrl-0 = <&i2c1_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&i2c2 { > + pinctrl-0 = <&i2c2_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&i2c3 { > + pinctrl-0 = <&i2c3_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&i2c6 { > + pinctrl-0 = <&i2c6_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&i2c7 { > + pinctrl-0 = <&i2c7_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&i2c8 { > + pinctrl-0 = <&i2c8_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > +}; > + > +&ostm0 { > + status = "okay"; > +}; > + > +&ostm1 { > + status = "okay"; > +}; > + > +&ostm2 { > + status = "okay"; > +}; > + > +&ostm3 { > + status = "okay"; > +}; > + > +&ostm4 { > + status = "okay"; > +}; > + > +&ostm5 { > + status = "okay"; > +}; > + > +&ostm6 { > + status = "okay"; > +}; > + > +&ostm7 { > + status = "okay"; > +}; > + > &pinctrl { > + i2c0_pins: i2c0 { > + pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */ > + <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */ > + }; > + > + i2c1_pins: i2c1 { > + pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */ > + <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */ > + }; > + > + i2c2_pins: i2c2 { > + pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */ > + <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */ > + }; > + > + i2c3_pins: i2c3 { > + pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */ > + <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */ > + }; > + > + i2c6_pins: i2c6 { > + pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */ > + <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */ > + }; > + > + i2c7_pins: i2c7 { > + pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */ > + <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */ > + }; > + > + i2c8_pins: i2c8 { > + pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */ > + <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ > + }; > + > scif_pins: scif { > pins = "SCIF_TXD", "SCIF_RXD"; > renesas,output-impedance = <1>; > }; > + > + sd1-pwr-en-hog { > + gpio-hog; > + gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>; > + output-high; > + line-name = "sd1_pwr_en"; > + }; > + > + sdhi1_pins: sd1 { > + sd1_data { > + pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3"; > + input-enable; > + renesas,output-impedance = <3>; > + slew-rate = <1>; > + }; > + > + sd1_cmd { > + pins = "SD1CMD"; > + input-enable; > + renesas,output-impedance = <3>; > + slew-rate = <1>; > + }; > + > + sd1_clk { > + pins = "SD1CLK"; > + renesas,output-impedance = <3>; > + slew-rate = <1>; > + }; > + > + sd1_cd { > + pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */ > + }; > + }; > }; > > &qextal_clk { > @@ -59,3 +238,15 @@ &scif { > > status = "okay"; > }; > + > +&sdhi1 { > + pinctrl-0 = <&sdhi1_pins>; > + pinctrl-1 = <&sdhi1_pins>; > + pinctrl-names = "default", "state_uhs"; > + vmmc-supply = <®_3p3v>; > + vqmmc-supply = <&vqmmc_sdhi1>; > + bus-width = <4>; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > + status = "okay"; > +}; > -- > 2.34.1
Hi Biju, On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > -----Original Message----- > > From: Prabhakar <prabhakar.csengg@gmail.com> > > Sent: Sunday, August 11, 2024 9:50 PM > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2 > > connector) on the RZ/V2H GP-EVK platform. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > - New patch > > --- > > .../boot/dts/renesas/r9a09g057h44-gp-evk.dts | 191 ++++++++++++++++++ > > 1 file changed, 191 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > index 593c48181248..11c13c85d278 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > @@ -7,6 +7,8 @@ > > > > /dts-v1/; > > > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > > +#include <dt-bindings/gpio/gpio.h> > > #include "r9a09g057.dtsi" > > > > / { > > @@ -14,6 +16,14 @@ / { > > compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; > > > > aliases { > > + i2c0 = &i2c0; > > + i2c1 = &i2c1; > > + i2c2 = &i2c2; > > + i2c3 = &i2c3; > > + i2c6 = &i2c6; > > + i2c7 = &i2c7; > > + i2c8 = &i2c8; > > + mmc1 = &sdhi1; > > serial0 = &scif; > > }; > > > > @@ -32,17 +42,186 @@ memory@240000000 { > > device_type = "memory"; > > reg = <0x2 0x40000000 0x2 0x00000000>; > > }; > > + > > + reg_3p3v: regulator1 { > > + compatible = "regulator-fixed"; > > + > > + regulator-name = "fixed-3.3V"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > + vqmmc_sdhi1: regulator-vccq-sdhi1 { > > + compatible = "regulator-gpio"; > > + regulator-name = "SDHI1 VccQ"; > > + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <3300000>; > > + gpios-states = <0>; > > + states = <3300000 0>, <1800000 1>; > > + }; > > }; > > > > &audio_extal_clk { > > clock-frequency = <22579200>; > > }; > > > > +&i2c0 { > > + pinctrl-0 = <&i2c0_pins>; > > + pinctrl-names = "default"; > > + > > + status = "okay"; > > +}; > > + > > clock-frequency = <100000>; in SoC dtsim > > Why frequency set to 100kHz for all the i2c nodes even though SoC supports > Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz? > This is due to driver limitation, once driver support for FM+ gets accepted [0] I plan to update the default frequency to !MHz in SoC DTSI. [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240711115207.2843133-9-claudiu.beznea.uj@bp.renesas.com/ Cheers, Prabhakar
Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: Monday, August 12, 2024 10:16 AM > Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI > > Hi Biju, > > On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > Hi Prabhakar, > > > > Thanks for the patch. > > > > > -----Original Message----- > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: Sunday, August 11, 2024 9:50 PM > > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: > > > Enable OSTM, I2C, and SDHI > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the > > > SD2 > > > connector) on the RZ/V2H GP-EVK platform. > > > > > > Signed-off-by: Lad Prabhakar > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > --- > > > v1->v2 > > > - New patch > > > --- > > > .../boot/dts/renesas/r9a09g057h44-gp-evk.dts | 191 > > > ++++++++++++++++++ > > > 1 file changed, 191 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > index 593c48181248..11c13c85d278 100644 > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > @@ -7,6 +7,8 @@ > > > > > > /dts-v1/; > > > > > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > > > +#include <dt-bindings/gpio/gpio.h> > > > #include "r9a09g057.dtsi" > > > > > > / { > > > @@ -14,6 +16,14 @@ / { > > > compatible = "renesas,gp-evk", "renesas,r9a09g057h44", > > > "renesas,r9a09g057"; > > > > > > aliases { > > > + i2c0 = &i2c0; > > > + i2c1 = &i2c1; > > > + i2c2 = &i2c2; > > > + i2c3 = &i2c3; > > > + i2c6 = &i2c6; > > > + i2c7 = &i2c7; > > > + i2c8 = &i2c8; > > > + mmc1 = &sdhi1; > > > serial0 = &scif; > > > }; > > > > > > @@ -32,17 +42,186 @@ memory@240000000 { > > > device_type = "memory"; > > > reg = <0x2 0x40000000 0x2 0x00000000>; > > > }; > > > + > > > + reg_3p3v: regulator1 { > > > + compatible = "regulator-fixed"; > > > + > > > + regulator-name = "fixed-3.3V"; > > > + regulator-min-microvolt = <3300000>; > > > + regulator-max-microvolt = <3300000>; > > > + regulator-boot-on; > > > + regulator-always-on; > > > + }; > > > + > > > + vqmmc_sdhi1: regulator-vccq-sdhi1 { > > > + compatible = "regulator-gpio"; > > > + regulator-name = "SDHI1 VccQ"; > > > + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; > > > + regulator-min-microvolt = <1800000>; > > > + regulator-max-microvolt = <3300000>; > > > + gpios-states = <0>; > > > + states = <3300000 0>, <1800000 1>; > > > + }; > > > }; > > > > > > &audio_extal_clk { > > > clock-frequency = <22579200>; > > > }; > > > > > > +&i2c0 { > > > + pinctrl-0 = <&i2c0_pins>; > > > + pinctrl-names = "default"; > > > + > > > + status = "okay"; > > > +}; > > > + > > > > clock-frequency = <100000>; in SoC dtsim > > > > Why frequency set to 100kHz for all the i2c nodes even though SoC > > supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz? > > > This is due to driver limitation, once driver support for FM+ gets accepted [0] I plan to update the > default frequency to !MHz in SoC DTSI. If there os no board limitation, please update to 400kHz, that is the next best frequency. Cheers, Biju > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240711115207.2843133-9- > claudiu.beznea.uj@bp.renesas.com/ > > Cheers, > Prabhakar
Hi Biju, On Mon, Aug 12, 2024 at 11:02 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Hi Prabhakar, > > > -----Original Message----- > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > Sent: Monday, August 12, 2024 10:16 AM > > Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI > > > > Hi Biju, > > > > On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > Hi Prabhakar, > > > > > > Thanks for the patch. > > > > > > > -----Original Message----- > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > Sent: Sunday, August 11, 2024 9:50 PM > > > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: > > > > Enable OSTM, I2C, and SDHI > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the > > > > SD2 > > > > connector) on the RZ/V2H GP-EVK platform. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > --- > > > > v1->v2 > > > > - New patch > > > > --- > > > > .../boot/dts/renesas/r9a09g057h44-gp-evk.dts | 191 > > > > ++++++++++++++++++ > > > > 1 file changed, 191 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > index 593c48181248..11c13c85d278 100644 > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > @@ -7,6 +7,8 @@ > > > > > > > > /dts-v1/; > > > > > > > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > > > > +#include <dt-bindings/gpio/gpio.h> > > > > #include "r9a09g057.dtsi" > > > > > > > > / { > > > > @@ -14,6 +16,14 @@ / { > > > > compatible = "renesas,gp-evk", "renesas,r9a09g057h44", > > > > "renesas,r9a09g057"; > > > > > > > > aliases { > > > > + i2c0 = &i2c0; > > > > + i2c1 = &i2c1; > > > > + i2c2 = &i2c2; > > > > + i2c3 = &i2c3; > > > > + i2c6 = &i2c6; > > > > + i2c7 = &i2c7; > > > > + i2c8 = &i2c8; > > > > + mmc1 = &sdhi1; > > > > serial0 = &scif; > > > > }; > > > > > > > > @@ -32,17 +42,186 @@ memory@240000000 { > > > > device_type = "memory"; > > > > reg = <0x2 0x40000000 0x2 0x00000000>; > > > > }; > > > > + > > > > + reg_3p3v: regulator1 { > > > > + compatible = "regulator-fixed"; > > > > + > > > > + regulator-name = "fixed-3.3V"; > > > > + regulator-min-microvolt = <3300000>; > > > > + regulator-max-microvolt = <3300000>; > > > > + regulator-boot-on; > > > > + regulator-always-on; > > > > + }; > > > > + > > > > + vqmmc_sdhi1: regulator-vccq-sdhi1 { > > > > + compatible = "regulator-gpio"; > > > > + regulator-name = "SDHI1 VccQ"; > > > > + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; > > > > + regulator-min-microvolt = <1800000>; > > > > + regulator-max-microvolt = <3300000>; > > > > + gpios-states = <0>; > > > > + states = <3300000 0>, <1800000 1>; > > > > + }; > > > > }; > > > > > > > > &audio_extal_clk { > > > > clock-frequency = <22579200>; > > > > }; > > > > > > > > +&i2c0 { > > > > + pinctrl-0 = <&i2c0_pins>; > > > > + pinctrl-names = "default"; > > > > + > > > > + status = "okay"; > > > > +}; > > > > + > > > > > > clock-frequency = <100000>; in SoC dtsim > > > > > > Why frequency set to 100kHz for all the i2c nodes even though SoC > > > supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz? > > > > > This is due to driver limitation, once driver support for FM+ gets accepted [0] I plan to update the > > default frequency to !MHz in SoC DTSI. > > If there os no board limitation, please update to 400kHz, that is the next best frequency. > I'll let Geert take a call on this as anyway the once the patch [0] will be merged we will update frequency to 1MHz. > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240711115207.2843133-9- > > claudiu.beznea.uj@bp.renesas.com/ > > Cheers, Prabhakar
Hi Prabhakar, > -----Original Message----- > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > Sent: Monday, August 12, 2024 1:29 PM > Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI > > Hi Biju, > > On Mon, Aug 12, 2024 at 11:02 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > Hi Prabhakar, > > > > > -----Original Message----- > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com> > > > Sent: Monday, August 12, 2024 10:16 AM > > > Subject: Re: [PATCH v2 7/8] arm64: dts: renesas: > > > r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI > > > > > > Hi Biju, > > > > > > On Mon, Aug 12, 2024 at 8:40 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > > > > > > > Hi Prabhakar, > > > > > > > > Thanks for the patch. > > > > > > > > > -----Original Message----- > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> > > > > > Sent: Sunday, August 11, 2024 9:50 PM > > > > > Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: > > > > > Enable OSTM, I2C, and SDHI > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on > > > > > the > > > > > SD2 > > > > > connector) on the RZ/V2H GP-EVK platform. > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > --- > > > > > v1->v2 > > > > > - New patch > > > > > --- > > > > > .../boot/dts/renesas/r9a09g057h44-gp-evk.dts | 191 > > > > > ++++++++++++++++++ > > > > > 1 file changed, 191 insertions(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > > b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > > index 593c48181248..11c13c85d278 100644 > > > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts > > > > > @@ -7,6 +7,8 @@ > > > > > > > > > > /dts-v1/; > > > > > > > > > > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> > > > > > +#include <dt-bindings/gpio/gpio.h> > > > > > #include "r9a09g057.dtsi" > > > > > > > > > > / { > > > > > @@ -14,6 +16,14 @@ / { > > > > > compatible = "renesas,gp-evk", "renesas,r9a09g057h44", > > > > > "renesas,r9a09g057"; > > > > > > > > > > aliases { > > > > > + i2c0 = &i2c0; > > > > > + i2c1 = &i2c1; > > > > > + i2c2 = &i2c2; > > > > > + i2c3 = &i2c3; > > > > > + i2c6 = &i2c6; > > > > > + i2c7 = &i2c7; > > > > > + i2c8 = &i2c8; > > > > > + mmc1 = &sdhi1; > > > > > serial0 = &scif; > > > > > }; > > > > > > > > > > @@ -32,17 +42,186 @@ memory@240000000 { > > > > > device_type = "memory"; > > > > > reg = <0x2 0x40000000 0x2 0x00000000>; > > > > > }; > > > > > + > > > > > + reg_3p3v: regulator1 { > > > > > + compatible = "regulator-fixed"; > > > > > + > > > > > + regulator-name = "fixed-3.3V"; > > > > > + regulator-min-microvolt = <3300000>; > > > > > + regulator-max-microvolt = <3300000>; > > > > > + regulator-boot-on; > > > > > + regulator-always-on; > > > > > + }; > > > > > + > > > > > + vqmmc_sdhi1: regulator-vccq-sdhi1 { > > > > > + compatible = "regulator-gpio"; > > > > > + regulator-name = "SDHI1 VccQ"; > > > > > + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; > > > > > + regulator-min-microvolt = <1800000>; > > > > > + regulator-max-microvolt = <3300000>; > > > > > + gpios-states = <0>; > > > > > + states = <3300000 0>, <1800000 1>; > > > > > + }; > > > > > }; > > > > > > > > > > &audio_extal_clk { > > > > > clock-frequency = <22579200>; }; > > > > > > > > > > +&i2c0 { > > > > > + pinctrl-0 = <&i2c0_pins>; > > > > > + pinctrl-names = "default"; > > > > > + > > > > > + status = "okay"; > > > > > +}; > > > > > + > > > > > > > > clock-frequency = <100000>; in SoC dtsim > > > > > > > > Why frequency set to 100kHz for all the i2c nodes even though SoC > > > > supports Transfer rate up to 1MHz? Is it board limitation restricting to 100kHz? > > > > > > > This is due to driver limitation, once driver support for FM+ gets > > > accepted [0] I plan to update the default frequency to !MHz in SoC DTSI. > > > > If there os no board limitation, please update to 400kHz, that is the next best frequency. > > > I'll let Geert take a call on this as anyway the once the patch [0] will be merged we will update > frequency to 1MHz. OK. Please make sure you don't set 1MHz for some devices like OV5645 which has a max transfer speed 400kHz. Cheers, Biju > > > > [0] > > > https://patchwork.kernel.org/project/linux-renesas-soc/patch/2024071 > > > 1115207.2843133-9- > > > claudiu.beznea.uj@bp.renesas.com/ > > > > Cheers, > Prabhakar
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts index 593c48181248..11c13c85d278 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> +#include <dt-bindings/gpio/gpio.h> #include "r9a09g057.dtsi" / { @@ -14,6 +16,14 @@ / { compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + mmc1 = &sdhi1; serial0 = &scif; }; @@ -32,17 +42,186 @@ memory@240000000 { device_type = "memory"; reg = <0x2 0x40000000 0x2 0x00000000>; }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c6 { + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c7 { + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&ostm3 { + status = "okay"; +}; + +&ostm4 { + status = "okay"; +}; + +&ostm5 { + status = "okay"; +}; + +&ostm6 { + status = "okay"; +}; + +&ostm7 { + status = "okay"; +}; + &pinctrl { + i2c0_pins: i2c0 { + pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */ + <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */ + }; + + i2c1_pins: i2c1 { + pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */ + <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */ + }; + + i2c2_pins: i2c2 { + pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */ + <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */ + <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */ + }; + + i2c6_pins: i2c6 { + pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */ + <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */ + }; + + i2c7_pins: i2c7 { + pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */ + <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */ + }; + + i2c8_pins: i2c8 { + pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */ + <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */ + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <1>; + }; + + sd1_cmd { + pins = "SD1CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <1>; + }; + + sd1_clk { + pins = "SD1CLK"; + renesas,output-impedance = <3>; + slew-rate = <1>; + }; + + sd1_cd { + pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */ + }; + }; }; &qextal_clk { @@ -59,3 +238,15 @@ &scif { status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +};