diff mbox series

[v3,6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

Message ID 20240821085644.240009-7-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform | expand

Commit Message

Lad, Prabhakar Aug. 21, 2024, 8:56 a.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- Grouped WDT nodes

v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

Comments

Geert Uytterhoeven Aug. 26, 2024, 12:21 p.m. UTC | #1 
Hi Prabhakar,

On Wed, Aug 21, 2024 at 10:56 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> - Grouped WDT nodes

Thanks for the update!

> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -201,6 +201,50 @@ ostm3: timer@14001000 {
>                         status = "disabled";
>                 };
>
> +               wdt0: watchdog@11c00400 {
> +                       compatible = "renesas,r9a09g057-wdt";
> +                       reg = <0 0x11c00400 0 0x400>;
> +                       clocks = <&cpg CPG_MOD 75>,
> +                                <&cpg CPG_MOD 76>;
> +                       clock-names = "pclk", "oscclk";
> +                       resets = <&cpg 117>;
> +                       power-domains = <&cpg>;
> +                       status = "disabled";
> +               };
> +
> +               wdt2: watchdog@13000000 {

Usually we sort the instances within a group by instance number, i.e.

    wdt0: watchdog@11c00400 {
    wdt1: watchdog@14400000 {
    wdt2: watchdog@13000000 {
    wdt3: watchdog@13000400 {

See e.g. the scif nodes in arch/arm64/boot/dts/renesas/r8a77951.dtsi:

    scif0: serial@e6e60000 {
    scif1: serial@e6e68000 {
    scif2: serial@e6e88000 {
    scif3: serial@e6c50000 {
    scif4: serial@e6c40000 {
    scif5: serial@e6f30000 {

scif3 and scif4 have lower base addresses than scif0.

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 9103335ac583..fb911780c4b4 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -201,6 +201,50 @@  ostm3: timer@14001000 {
 			status = "disabled";
 		};
 
+		wdt0: watchdog@11c00400 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x11c00400 0 0x400>;
+			clocks = <&cpg CPG_MOD 75>,
+				 <&cpg CPG_MOD 76>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 117>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@13000000 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x13000000 0 0x400>;
+			clocks = <&cpg CPG_MOD 79>,
+				 <&cpg CPG_MOD 80>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 119>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@13000400 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x13000400 0 0x400>;
+			clocks = <&cpg CPG_MOD 81>,
+				 <&cpg CPG_MOD 82>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 120>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@14400000 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x14400000 0 0x400>;
+			clocks = <&cpg CPG_MOD 77>,
+				 <&cpg CPG_MOD 78>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 118>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c8: i2c@11c01000 {
 			compatible = "renesas,riic-r9a09g057";
 			reg = <0 0x11c01000 0 0x400>;