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AJvYcCUBmNNLtw8L+fM1hbWWxMyxrSoPuhGeiJeLCTZsKAvqv7QmD7JbQUNmSWziPbBrojH3iGWK2hHlXTE+@vger.kernel.org, AJvYcCX1/h8yv1oKosQqdFD0cESe3DNFfOWq0ewfuAZIaQB4KPKHNxm2+BQ0TNL2JnvRYc9N154nxG5sBy8kwIwD@vger.kernel.org X-Gm-Message-State: AOJu0Yz8FbXT9468nzJJzzgGhKfMm2JgXIkXr7TtpH1qKORJ+BQZeaQq ARsgsLMfxpwb0f2o4jdfyxcRbT0QkzVzSfN6dn8DlNma6YplEmv9 X-Google-Smtp-Source: AGHT+IFSz13Q818Zqi9BjvyCiTrajFKSoOM83UG3yaOZkPmn8FUtSGh3w2GhUWxs8PMeRJt4vgL1/Q== X-Received: by 2002:a17:907:7252:b0:a86:43c0:7d2 with SMTP id a640c23a62f3a-a866ee6476cmr141315966b.0.1724230616751; Wed, 21 Aug 2024 01:56:56 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:b9a9:40a4:353f:6481]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83838cf183sm873416266b.56.2024.08.21.01.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 01:56:56 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 7/8] arm64: dts: renesas: r9a09g057h44-gp-evk: Enable OSTM, I2C, and SDHI Date: Wed, 21 Aug 2024 09:56:43 +0100 Message-Id: <20240821085644.240009-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240821085644.240009-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240821085644.240009-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2 connector) on the RZ/V2H GP-EVK platform. Signed-off-by: Lad Prabhakar --- note, for i2c nodes we are defaulting the clock-frequency and this will be updated when slave nodes are enabled. v2->v3 - Set the default slew reset value for SDHI1 pins v1->v2 - New patch --- .../boot/dts/renesas/r9a09g057h44-gp-evk.dts | 184 ++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts index 593c48181248..1c532810dad0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-gp-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include "r9a09g057.dtsi" / { @@ -14,6 +16,14 @@ / { compatible = "renesas,gp-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + mmc1 = &sdhi1; serial0 = &scif; }; @@ -32,17 +42,179 @@ memory@240000000 { device_type = "memory"; reg = <0x2 0x40000000 0x2 0x00000000>; }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c6 { + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c7 { + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&ostm3 { + status = "okay"; +}; + +&ostm4 { + status = "okay"; +}; + +&ostm5 { + status = "okay"; +}; + +&ostm6 { + status = "okay"; +}; + +&ostm7 { + status = "okay"; +}; + &pinctrl { + i2c0_pins: i2c0 { + pinmux = , /* I2C0_SDA */ + ; /* I2C0_SCL */ + }; + + i2c1_pins: i2c1 { + pinmux = , /* I2C1_SDA */ + ; /* I2C1_SCL */ + }; + + i2c2_pins: i2c2 { + pinmux = , /* I2C2_SDA */ + ; /* I2C2_SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ + }; + + i2c6_pins: i2c6 { + pinmux = , /* I2C6_SDA */ + ; /* I2C6_SCL */ + }; + + i2c7_pins: i2c7 { + pinmux = , /* I2C7_SDA */ + ; /* I2C7_SCL */ + }; + + i2c8_pins: i2c8 { + pinmux = , /* I2C8_SDA */ + ; /* I2C8_SCL */ + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_dat_cmd { + pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd1_clk { + pins = "SD1CLK"; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd1_cd { + pinmux = ; /* SD1_CD */ + }; + }; }; &qextal_clk { @@ -59,3 +231,15 @@ &scif { status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +};