| Message ID | 20240828124134.188864-8-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 095105496e7dde554aa3dc01189779759d976c2d |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for Renesas RZ/V2H(P) SoC and RZV2H-EVK platform | expand |
On Wed, Aug 28, 2024 at 2:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v3->v4 > - Used hexadecimal values for clocks and resets > - Sorted nodes based on nodes index Thanks, will queue in renesas-devel for v6.12. > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > @@ -201,6 +201,50 @@ ostm7: timer@12c03000 { > status = "disabled"; > }; > > + wdt0: watchdog@11c00400 { > + compatible = "renesas,r9a09g057-wdt"; > + reg = <0 0x11c00400 0 0x400>; > + clocks = <&cpg CPG_MOD 0x4b>, > + <&cpg CPG_MOD 0x4c>; This fits on a single line, so I will reformat while applying. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 7e243c127ec2..4071deabae42 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -201,6 +201,50 @@ ostm7: timer@12c03000 { status = "disabled"; }; + wdt0: watchdog@11c00400 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x11c00400 0 0x400>; + clocks = <&cpg CPG_MOD 0x4b>, + <&cpg CPG_MOD 0x4c>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x75>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@14400000 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x14400000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, + <&cpg CPG_MOD 0x4e>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x76>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@13000000 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x13000000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4f>, + <&cpg CPG_MOD 0x50>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x77>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@13000400 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x13000400 0 0x400>; + clocks = <&cpg CPG_MOD 0x51>, + <&cpg CPG_MOD 0x52>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x78>; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>;