diff mbox series

[2/2] arm64: dts: renesas: r8a779h0: gray-hawk-single: Enable PCIe Host

Message ID 20240904003409.1578212-3-yoshihiro.shimoda.uh@renesas.com (mailing list archive)
State Mainlined
Commit 951f7eb0c2358b51ce782942df6c880da57f8882
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: r8a779h0: Enable PCIe Host | expand

Commit Message

Yoshihiro Shimoda Sept. 4, 2024, 12:34 a.m. UTC
Enable PCIe Host controller on R-Car V4M Gray Hawk board.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 .../dts/renesas/r8a779h0-gray-hawk-single.dts | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Geert Uytterhoeven Sept. 25, 2024, 3:43 p.m. UTC | #1
On Wed, Sep 4, 2024 at 2:34 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Enable PCIe Host controller on R-Car V4M Gray Hawk board.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.13.

> --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts

> +&pciec0 {
> +       reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>;

reset-gpios

The former was deprecated in commit 42694f9f6407a933 ("dt-bindings:
PCI: add snps,dw-pcie.yaml").

I'll fix that up while applying.

> +       status = "okay";
> +};
> +
>  &pfc {
>         pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>;
>         pinctrl-names = "default";

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
index 9a1917b87f61..a5faff87aa26 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
@@ -126,6 +126,12 @@  memory@480000000 {
 		reg = <0x4 0x80000000 0x1 0x80000000>;
 	};
 
+	pcie_clk: clk-9fgv0841-pci {
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+		#clock-cells = <0>;
+	};
+
 	reg_1p8v: regulator-1p8v {
 			compatible = "regulator-fixed";
 			regulator-name = "fixed-1.8V";
@@ -240,6 +246,17 @@  &i2c0 {
 	status = "okay";
 	clock-frequency = <400000>;
 
+	io_expander_a: gpio@20 {
+		compatible = "onnn,pca9654";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	eeprom@50 {
 		compatible = "rohm,br24g01", "atmel,24c01";
 		label = "cpu-board";
@@ -309,6 +326,18 @@  &mmc0 {
 	status = "okay";
 };
 
+&pcie0_clkref {
+	compatible = "gpio-gate-clock";
+	clocks = <&pcie_clk>;
+	enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+	/delete-property/ clock-frequency;
+};
+
+&pciec0 {
+	reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>;
 	pinctrl-names = "default";