From patchwork Wed Nov 6 08:17:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13864017 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1830C1D435F for ; Wed, 6 Nov 2024 08:19:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730881160; cv=none; b=Cw5cQ/I9SFYEMJUfc5WvgMbeivvZmqZQT/4AtJTDNxcryH9x9RAohsO5wKalM4SqzT4gHVYJ0EvDS05PIV5JeRgrCVwTPVbnGS2JuEaPwQ3mEAsJ81cVvlPP61HfysO0pqHJz8AJMl5VitTHYXQVvYmqWYVA942P+tCCu6xYKHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730881160; c=relaxed/simple; bh=wIAZhI2L7AgNlpk7R2kynKKgko0xrLuPdmEQFFDuRHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hm/VPqcBui2GmWRSIO1qPf6LEPj+pZGdQEdQjE/FSMZIoqBpyFATyi/kaKeeMSTbMw/xSvEqMWbk320iV8alLlxlRzRegC09SuLe22LQaEpTncUykJFwWso/CSIrJV2AsydpGEMiccdXfO5Ow9kGYmC6RbJw3hOJPiBAujXoaS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=TuBmwVHJ; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="TuBmwVHJ" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-a9eb3794a04so232214066b.3 for ; Wed, 06 Nov 2024 00:19:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1730881157; x=1731485957; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UjZyRFf+ggCRDSZ/jRiaVjDROYmGDQ4TjBntpQqqtgQ=; b=TuBmwVHJJjKMjMPK5FwNkSDgoY7LGZgBkDKktZyNu6u1x5/FFsQsNRv4TfmCmZC7vz hhDycFpnhhXPuoI8V9AdaMtXi4DoruSPgKhQr6vXvy6zmJdYZEAAJtQvF2y3jetJdQ81 HBW1O5dz7dwVO0AJUE16cGe4YH6RgYxNbCbYJ1wH//XI9Zg5qHwOWLAk8ElUYx60Texu 0Z+ADON06bhEQHtd7aXBLvmqtp1qIlddfiVIO8riA1eSZV05k75dmIiN3qnF1vu3cPz8 crppaMZDx8UU1CwilDwC9MdeGOrS/yuV4a4sI5L4DfQXwU36iMzwqC9oP7P3u3xdrPC5 4ICg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730881157; x=1731485957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UjZyRFf+ggCRDSZ/jRiaVjDROYmGDQ4TjBntpQqqtgQ=; b=Eyfe9dmU+Bx76FBPq7/wPscANsNZ76rSdxNBTupM/Dr7yS2pBp3aTlz76A9GtrfBw8 yQ3QrW8m7gjfFnBdFMYL+ABYkqQrurBjYCZkyl5VlpOM/YXF8+gcNwckdike7mHtoZbc u0ac3d0DeNdcByNdIRYFbnci6PiWDEqL5CTXZ72kWz5803218y8u+nT/yzVxg+h9mOY1 RLAr3YjJwrurd+tYduMOCWENNm6MMH73Uujm3m2IsfIEe19T0e9H92vlIAoH6t1p6NWP PBYERV3e31lPyp+Bi/qfl8nAqiCznyceQ0/KCmqgjHtVvOYK7HKHcazfY4htc2updZtn jR5A== X-Gm-Message-State: AOJu0Yws8rWwFzmwBcVwpA1fYAYRZlpOaogTmReS/YREKHMTM4u2UtII IohvhjD7LAhEg4imS0Ch3Q4JbNwuPzWfcxrHcvRqQqfIby3xXumcgaZ5bJrJ+eo= X-Google-Smtp-Source: AGHT+IHc1SBa37Zc5hY9x9+xd6Yuiv0kIPY8lGcBBjtgyaTbmjEF6WHAwoybgZOFTyUf7zxelOPZbg== X-Received: by 2002:a17:907:7e8b:b0:a9a:3cec:b322 with SMTP id a640c23a62f3a-a9e3a6c99e0mr2395311166b.45.1730881157192; Wed, 06 Nov 2024 00:19:17 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb16a2dbcsm241369766b.40.2024.11.06.00.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 00:19:16 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, lgirdwood@gmail.com, broonie@kernel.org, magnus.damm@gmail.com, linus.walleij@linaro.org, support.opensource@diasemi.com, perex@perex.cz, tiwai@suse.com, p.zabel@pengutronix.de, Adam.Thomson.Opensource@diasemi.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH 01/31] clk: renesas: r9a08g045-cpg: Add clocks, resets and power domains support for SSI Date: Wed, 6 Nov 2024 10:17:56 +0200 Message-Id: <20241106081826.1211088-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241106081826.1211088-1-claudiu.beznea.uj@bp.renesas.com> References: <20241106081826.1211088-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add SSI clocks, resets and power domains support for the SSI blocks available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index b2ae8cdc4723..d71e77624fac 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -209,6 +209,14 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), + DEF_MOD("ssi0_pclk", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0), + DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1), + DEF_MOD("ssi1_pclk", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2), + DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3), + DEF_MOD("ssi2_pclk", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4), + DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5), + DEF_MOD("ssi3_pclk", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6), + DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7), DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0), DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1), DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2), @@ -238,6 +246,10 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), + DEF_RST(R9A08G045_SSI0_RST_M2_REG, 0x870, 0), + DEF_RST(R9A08G045_SSI1_RST_M2_REG, 0x870, 1), + DEF_RST(R9A08G045_SSI2_RST_M2_REG, 0x870, 2), + DEF_RST(R9A08G045_SSI3_RST_M2_REG, 0x870, 3), DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0), DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1), DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2), @@ -286,6 +298,14 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0), DEF_PD("sdhi2", R9A08G045_PD_SDHI2, DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0), + DEF_PD("ssi0", R9A08G045_PD_SSI0, + DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(10)), 0), + DEF_PD("ssi1", R9A08G045_PD_SSI1, + DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(11)), 0), + DEF_PD("ssi2", R9A08G045_PD_SSI2, + DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(12)), 0), + DEF_PD("ssi3", R9A08G045_PD_SSI3, + DEF_REG_CONF(CPG_BUS_MCPU1_MSTOP, BIT(13)), 0), DEF_PD("usb0", R9A08G045_PD_USB0, DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)), 0), DEF_PD("usb1", R9A08G045_PD_USB1,