[05/31] pinctrl: renesas: rzg2l: Add audio clock pins

Message ID	20241106081826.1211088-6-claudiu.beznea.uj@bp.renesas.com (mailing list archive)
State	New
Delegated to:	Geert Uytterhoeven
Headers	show Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFC001D90C5 for <linux-renesas-soc@vger.kernel.org>; Wed, 6 Nov 2024 08:19:27 +0000 (UTC) From: Claudiu <claudiu.beznea@tuxon.dev> To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, lgirdwood@gmail.com, broonie@kernel.org, magnus.damm@gmail.com, linus.walleij@linaro.org, support.opensource@diasemi.com, perex@perex.cz, tiwai@suse.com, p.zabel@pengutronix.de, Adam.Thomson.Opensource@diasemi.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 05/31] pinctrl: renesas: rzg2l: Add audio clock pins Date: Wed, 6 Nov 2024 10:18:00 +0200 Message-Id: <20241106081826.1211088-6-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20241106081826.1211088-1-claudiu.beznea.uj@bp.renesas.com> References: <20241106081826.1211088-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add audio support for the Renesas RZ/G3S SoC \| expand [00/31] Add audio support for the Renesas RZ/G3S SoC [01/31] clk: renesas: r9a08g045-cpg: Add clocks, resets and power domains support for SSI [02/31] clk: versaclock3: Prepare for the addition of 5L35023 device [03/31] dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator [04/31] clk: versaclock3: Add support for the 5L35023 variant [05/31] pinctrl: renesas: rzg2l: Add audio clock pins [06/31] ASoC: sh: rz-ssi: Terminate all the DMA transactions [07/31] ASoC: sh: rz-ssi: Use only the proper amount of dividers [08/31] ASoC: sh: rz-ssi: Fix typo on SSI_RATES macro comment [09/31] ASoC: sh: rz-ssi: Remove pdev member of struct rz_ssi_priv [10/31] ASoC: sh: rz-ssi: Remove the rz_ssi_get_dai() function [11/31] ASoC: sh: rz-ssi: Remove the 2nd argument of rz_ssi_stream_is_play() [12/31] ASoC: sh: rz-ssi: Use a proper bitmask for clear bits [13/31] ASoC: sh: rz-ssi: Use readl_poll_timeout_atomic() [14/31] ASoC: sh: rz-ssi: Use temporary variable for struct device [15/31] ASoC: sh: rz-ssi: Use goto label names that specify their actions [16/31] ASoC: sh: rz-ssi: Rely on the ASoC subsystem to runtime resume/suspend the SSI [17/31] ASoC: sh: rz-ssi: Enable runtime PM autosuspend support [18/31] ASoC: sh: rz-ssi: Add runtime PM support [19/31] ASoC: sh: rz-ssi: Issue software reset in hw_params API [20/31] ASoC: sh: rz-ssi: Add suspend to RAM support [21/31] ASoC: dt-bindings: renesas,rz-ssi: Document the Renesas RZ/G3S SoC [22/31] ASoC: da7213: Populate max_register to regmap_config [23/31] ASoC: da7213: Return directly the value of regcache_sync() [24/31] ASoC: da7213: Add suspend to RAM support [25/31] ASoC: da7213: Avoid setting PLL when closing audio stream [26/31] ASoC: da7213: Extend support for the MCK in range [2, 50] MHz [27/31] arm64: dts: renesas: r9a08g045: Add SSI nodes [28/31] arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node [29/31] arm64: dts: renesas: Add da7212 audio codec node [30/31] arm64: dts: renesas: rzg3s-smarc: Enable SSI3 [31/31] arm64: dts: renesas: rzg3s-smarc: Add sound card

Message ID

20241106081826.1211088-6-claudiu.beznea.uj@bp.renesas.com (mailing list archive)

State

New

Delegated to:

Geert Uytterhoeven

Headers

From: Claudiu <claudiu.beznea@tuxon.dev>
To: geert+renesas@glider.be,
	mturquette@baylibre.com,
	sboyd@kernel.org,
	robh@kernel.org,
	krzk+dt@kernel.org,
	conor+dt@kernel.org,
	biju.das.jz@bp.renesas.com,
	prabhakar.mahadev-lad.rj@bp.renesas.com,
	lgirdwood@gmail.com,
	broonie@kernel.org,
	magnus.damm@gmail.com,
	linus.walleij@linaro.org,
	support.opensource@diasemi.com,
	perex@perex.cz,
	tiwai@suse.com,
	p.zabel@pengutronix.de,
	Adam.Thomson.Opensource@diasemi.com
Cc: linux-renesas-soc@vger.kernel.org,
	linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-sound@vger.kernel.org,
	linux-gpio@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH 05/31] pinctrl: renesas: rzg2l: Add audio clock pins
Date: Wed,  6 Nov 2024 10:18:00 +0200
Message-Id: <20241106081826.1211088-6-claudiu.beznea.uj@bp.renesas.com>
In-Reply-To: <20241106081826.1211088-1-claudiu.beznea.uj@bp.renesas.com>
References: <20241106081826.1211088-1-claudiu.beznea.uj@bp.renesas.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add audio support for the Renesas RZ/G3S SoC | expand

Commit Message

Claudiu Beznea Nov. 6, 2024, 8:18 a.m. UTC

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add audio clock pins. These are used by audio IPs as input pins to feed
them with audio clocks.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 8ffb9430a134..1190ca4b1808 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2086,6 +2086,8 @@  static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
 						      PIN_CFG_SOFT_PS)) },
 	{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
 	{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
+	{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
+	{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
 	{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
 	{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
 						     PIN_CFG_IO_VMC_SD0)) },

[05/31] pinctrl: renesas: rzg2l: Add audio clock pins

Commit Message

Patch