diff mbox series

clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI

Message ID 20250104175346.656352-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI | expand

Commit Message

Lad, Prabhakar Jan. 4, 2025, 5:53 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add clock and reset entries for the DRP-AI block, which is available only
on the Renesas RZ/V2L SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 53 +++++++++++++++++++++++++++--
 drivers/clk/renesas/rzg2l-cpg.h     |  2 ++
 2 files changed, 53 insertions(+), 2 deletions(-)

Comments

kernel test robot Jan. 6, 2025, 3:10 a.m. UTC | #1 
Hi Prabhakar,

kernel test robot noticed the following build warnings:

[auto build test WARNING on geert-renesas-drivers/renesas-clk]
[also build test WARNING on clk/clk-next linus/master v6.13-rc6 next-20241220]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-r9a07g044-Add-clock-and-reset-entry-for-DRP-AI/20250105-015708
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link:    https://lore.kernel.org/r/20250104175346.656352-1-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH] clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
config: nios2-randconfig-r052-20250106 (https://download.01.org/0day-ci/archive/20250106/202501061001.6iClUTxN-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250106/202501061001.6iClUTxN-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501061001.6iClUTxN-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/renesas/r9a07g044-cpg.c:97:35: warning: 'dtable_4_32' defined but not used [-Wunused-const-variable=]
      97 | static const struct clk_div_table dtable_4_32[] = {
         |                                   ^~~~~~~~~~~


vim +/dtable_4_32 +97 drivers/clk/renesas/r9a07g044-cpg.c

    96	
  > 97	static const struct clk_div_table dtable_4_32[] = {
    98		{3, 4},
    99		{4, 5},
   100		{5, 6},
   101		{6, 7},
   102		{7, 8},
   103		{8, 9},
   104		{9, 10},
   105		{10, 11},
   106		{11, 12},
   107		{12, 13},
   108		{13, 14},
   109		{14, 15},
   110		{15, 16},
   111		{16, 17},
   112		{17, 18},
   113		{18, 19},
   114		{19, 20},
   115		{20, 21},
   116		{21, 22},
   117		{22, 23},
   118		{23, 24},
   119		{24, 25},
   120		{25, 26},
   121		{26, 27},
   122		{27, 28},
   123		{28, 29},
   124		{29, 30},
   125		{30, 31},
   126		{31, 32},
   127		{0, 0},
   128	};
   129
Lad, Prabhakar Jan. 6, 2025, 8:24 p.m. UTC | #2 
Hi,

Thank you for the report.

On Mon, Jan 6, 2025 at 3:11 AM kernel test robot <lkp@intel.com> wrote:
>
> Hi Prabhakar,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on geert-renesas-drivers/renesas-clk]
> [also build test WARNING on clk/clk-next linus/master v6.13-rc6 next-20241220]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url:    https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-r9a07g044-Add-clock-and-reset-entry-for-DRP-AI/20250105-015708
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
> patch link:    https://lore.kernel.org/r/20250104175346.656352-1-prabhakar.mahadev-lad.rj%40bp.renesas.com
> patch subject: [PATCH] clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
> config: nios2-randconfig-r052-20250106 (https://download.01.org/0day-ci/archive/20250106/202501061001.6iClUTxN-lkp@intel.com/config)
> compiler: nios2-linux-gcc (GCC) 14.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250106/202501061001.6iClUTxN-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202501061001.6iClUTxN-lkp@intel.com/
>
> All warnings (new ones prefixed by >>):
>
> >> drivers/clk/renesas/r9a07g044-cpg.c:97:35: warning: 'dtable_4_32' defined but not used [-Wunused-const-variable=]
>       97 | static const struct clk_div_table dtable_4_32[] = {
>          |                                   ^~~~~~~~~~~
>
>
> vim +/dtable_4_32 +97 drivers/clk/renesas/r9a07g044-cpg.c
>
>     96
>   > 97  static const struct clk_div_table dtable_4_32[] = {
>     98          {3, 4},
>     99          {4, 5},
>    100          {5, 6},
>    101          {6, 7},
>    102          {7, 8},
>    103          {8, 9},
>    104          {9, 10},
>    105          {10, 11},
>    106          {11, 12},
>    107          {12, 13},
>    108          {13, 14},
>    109          {14, 15},
>    110          {15, 16},
>    111          {16, 17},
>    112          {17, 18},
>    113          {18, 19},
>    114          {19, 20},
>    115          {20, 21},
>    116          {21, 22},
>    117          {22, 23},
>    118          {23, 24},
>    119          {24, 25},
>    120          {25, 26},
>    121          {26, 27},
>    122          {27, 28},
>    123          {28, 29},
>    124          {29, 30},
>    125          {30, 31},
>    126          {31, 32},
>    127          {0, 0},
>    128  };
>    129
>
I'll guard the above with #ifdef CONFIG_CLK_R9A07G054.

Cheers,
Prabhakar
kernel test robot Jan. 6, 2025, 8:45 p.m. UTC | #3 
Hi Prabhakar,

kernel test robot noticed the following build warnings:

[auto build test WARNING on geert-renesas-drivers/renesas-clk]
[also build test WARNING on clk/clk-next linus/master v6.13-rc6 next-20250106]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-r9a07g044-Add-clock-and-reset-entry-for-DRP-AI/20250105-015708
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link:    https://lore.kernel.org/r/20250104175346.656352-1-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH] clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
config: mips-randconfig-r073-20250107 (https://download.01.org/0day-ci/archive/20250107/202501070453.pzWqNQZr-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250107/202501070453.pzWqNQZr-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501070453.pzWqNQZr-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/renesas/r9a07g044-cpg.c:97:35: warning: unused variable 'dtable_4_32' [-Wunused-const-variable]
      97 | static const struct clk_div_table dtable_4_32[] = {
         |                                   ^~~~~~~~~~~
   1 warning generated.


vim +/dtable_4_32 +97 drivers/clk/renesas/r9a07g044-cpg.c

    96	
  > 97	static const struct clk_div_table dtable_4_32[] = {
    98		{3, 4},
    99		{4, 5},
   100		{5, 6},
   101		{6, 7},
   102		{7, 8},
   103		{8, 9},
   104		{9, 10},
   105		{10, 11},
   106		{11, 12},
   107		{12, 13},
   108		{13, 14},
   109		{14, 15},
   110		{15, 16},
   111		{16, 17},
   112		{17, 18},
   113		{18, 19},
   114		{19, 20},
   115		{20, 21},
   116		{21, 22},
   117		{22, 23},
   118		{23, 24},
   119		{24, 25},
   120		{25, 26},
   121		{26, 27},
   122		{27, 28},
   123		{28, 29},
   124		{29, 30},
   125		{30, 31},
   126		{31, 32},
   127		{0, 0},
   128	};
   129
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index d5979270f4ae..ac86bfdb70aa 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -95,6 +95,39 @@  static const struct clk_div_table dtable_1_32[] = {
 	{0, 0},
 };
 
+static const struct clk_div_table dtable_4_32[] = {
+	{3, 4},
+	{4, 5},
+	{5, 6},
+	{6, 7},
+	{7, 8},
+	{8, 9},
+	{9, 10},
+	{10, 11},
+	{11, 12},
+	{12, 13},
+	{13, 14},
+	{14, 15},
+	{15, 16},
+	{16, 17},
+	{17, 18},
+	{18, 19},
+	{19, 20},
+	{20, 21},
+	{21, 22},
+	{22, 23},
+	{23, 24},
+	{24, 25},
+	{25, 26},
+	{26, 27},
+	{27, 28},
+	{28, 29},
+	{29, 30},
+	{30, 31},
+	{31, 32},
+	{0, 0},
+};
+
 static const struct clk_div_table dtable_16_128[] = {
 	{0, 16},
 	{1, 32},
@@ -115,7 +148,7 @@  static const u32 mtable_sdhi[] = { 1, 2, 3 };
 static const struct {
 	struct cpg_core_clk common[56];
 #ifdef CONFIG_CLK_R9A07G054
-	struct cpg_core_clk drp[0];
+	struct cpg_core_clk drp[3];
 #endif
 } core_clks __initconst = {
 	.common = {
@@ -193,6 +226,9 @@  static const struct {
 	},
 #ifdef CONFIG_CLK_R9A07G054
 	.drp = {
+		DEF_FIXED("DRP_M", R9A07G054_CLK_DRP_M, CLK_PLL3, 1, 5),
+		DEF_FIXED("DRP_D", R9A07G054_CLK_DRP_D, CLK_PLL3, 1, 2),
+		DEF_DIV("DRP_A", R9A07G054_CLK_DRP_A, CLK_PLL3, DIVPL3E, dtable_4_32),
 	},
 #endif
 };
@@ -200,7 +236,7 @@  static const struct {
 static const struct {
 	struct rzg2l_mod_clk common[79];
 #ifdef CONFIG_CLK_R9A07G054
-	struct rzg2l_mod_clk drp[0];
+	struct rzg2l_mod_clk drp[5];
 #endif
 } mod_clks = {
 	.common = {
@@ -365,6 +401,16 @@  static const struct {
 	},
 #ifdef CONFIG_CLK_R9A07G054
 	.drp = {
+		DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK,
+					0x5e8, 0),
+		DEF_MOD("stpai_aclk",	R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1,
+					0x5e8, 1),
+		DEF_MOD("stpai_mclk",	R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M,
+					0x5e8, 2),
+		DEF_MOD("stpai_dclkin",	R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D,
+					0x5e8, 3),
+		DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A,
+					0x5e8, 4),
 	},
 #endif
 };
@@ -431,6 +477,9 @@  static const struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
 	DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
 	DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
+#ifdef CONFIG_CLK_R9A07G054
+	DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0),
+#endif
 };
 
 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 975a8e09f7d3..e2743201102f 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -21,6 +21,7 @@ 
 #define CPG_PL2_DDIV		(0x204)
 #define CPG_PL3A_DDIV		(0x208)
 #define CPG_PL6_DDIV		(0x210)
+#define CPG_PL3C_SDIV		(0x214)
 #define CPG_CLKSTATUS		(0x280)
 #define CPG_PL3_SSEL		(0x408)
 #define CPG_PL6_SSEL		(0x414)
@@ -71,6 +72,7 @@ 
 #define DIVPL3A		DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
 #define DIVPL3B		DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
 #define DIVPL3C		DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
+#define DIVPL3E		DDIV_PACK(CPG_PL3C_SDIV, 8, 5)
 #define DIVGPU		DDIV_PACK(CPG_PL6_DDIV, 0, 2)
 
 #define SEL_PLL_PACK(offset, bitpos, size) \