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Mon, 13 Jan 2025 03:24:02 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:acc9:404c:3a6c:d1aa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436f04df606sm107597115e9.12.2025.01.13.03.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 03:24:01 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 4/6] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property Date: Mon, 13 Jan 2025 11:23:47 +0000 Message-ID: <20250113112349.801875-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The RZ/V2H(P) CPG block includes Error Reset Registers (CPG_ERROR_RSTm). A system reset is triggered in response to error interrupt factors, and the corresponding bit is set in the CPG_ERROR_RSTm register. These registers can be utilized by various IP blocks as needed. In the event of a watchdog overflow or underflow, a system reset is issued, and the CPG_ERROR_RST2[0/1/2/3] bits are set depending on the watchdog in use: CM33 = 0, CA55 = 1, CR8_0 = 2, CR8_1 = 3. For the watchdog driver to determine and report the current boot status, it needs to read the CPG_ERROR_RST2[0/1/2/3]bits and provide this information to the user upon request. To facilitate this operation, add `renesas,syscon-cpg-error-rst` property to the WDT node, which maps to the `syscon` CPG node, enabling retrieval of the necessary information. Additionally, the property is marked as required for the RZ/V2H(P) SoC to ensure future compatibility (e.g., where the same IP block is present on the RZ/G3E SoC) and explicitly disallowed for other SoCs. Signed-off-by: Lad Prabhakar --- Note, this change doesnt break any ABI, as the subsequent driver patch handles the case elegantly if the `syscon` node is missing to handle backward compatibility. v2->v3 - No change v1->v2 - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst` - Updated commit message --- .../bindings/watchdog/renesas,wdt.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 29ada89fdcdc..ca62ae8b1b0c 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -112,6 +112,19 @@ properties: timeout-sec: true + renesas,syscon-cpg-error-rst: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The first cell is a phandle to the SYSCON entry required to obtain + the current boot status. The second cell specifies the CPG_ERROR_RSTm + register offset within the SYSCON, and the third cell indicates the + bit within the CPG_ERROR_RSTm register. + items: + - items: + - description: Phandle to the CPG node + - description: The CPG_ERROR_RSTm register offset + - description: The bit within CPG_ERROR_RSTm register of interest + required: - compatible - reg @@ -182,7 +195,11 @@ allOf: properties: interrupts: false interrupt-names: false + required: + - renesas,syscon-cpg-error-rst else: + properties: + renesas,syscon-cpg-error-rst: false required: - interrupts