| Message ID | 20250131112429.119882-5-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add RZ/G3E SDHI support | expand |
Hi Biju, On Fri, 31 Jan 2025 at 12:25, Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add SDHI0-SDHI2 nodes to RZ/G3E ("R9A09G047") SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v1->v2: > * Status of internal regulator is disabled in the SoC .dtsi. Override > the status in the board DTS when needed. Thanks for the update! > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > @@ -410,6 +410,66 @@ gic: interrupt-controller@14900000 { > interrupt-controller; > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > }; > + > + sdhi0: mmc@15c00000 { > + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; > + reg = <0x0 0x15c00000 0 0x10000>; > + interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, > + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; > + clock-names = "core", "clkh", "cd", "aclk"; > + resets = <&cpg 0xa7>; > + power-domains = <&cpg>; > + status = "disabled"; > + > + vqmmc_sdhi0: vqmmc-regulator { sdhi0_vqmmc? (same for the others) > + regulator-name = "SDHI0-VQMMC"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + status = "disabled"; > + }; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert Uytterhoeven, > -----Original Message----- > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: 05 February 2025 08:17 > Subject: Re: [PATCH v2 4/8] arm64: dts: renesas: r9a09g047: Add SDHI0-SDHI2 nodes > > Hi Biju, > > On Fri, 31 Jan 2025 at 12:25, Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Add SDHI0-SDHI2 nodes to RZ/G3E ("R9A09G047") SoC DTSI. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v1->v2: > > * Status of internal regulator is disabled in the SoC .dtsi. Override > > the status in the board DTS when needed. > > Thanks for the update! > > > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi > > @@ -410,6 +410,66 @@ gic: interrupt-controller@14900000 { > > interrupt-controller; > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; > > }; > > + > > + sdhi0: mmc@15c00000 { > > + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; > > + reg = <0x0 0x15c00000 0 0x10000>; > > + interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, > > + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; > > + clock-names = "core", "clkh", "cd", "aclk"; > > + resets = <&cpg 0xa7>; > > + power-domains = <&cpg>; > > + status = "disabled"; > > + > > + vqmmc_sdhi0: vqmmc-regulator { > > sdhi0_vqmmc? (same for the others) It is ok to me. Cheers, Biju
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index c93aa16d0a6e..8d4717d4cf14 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -410,6 +410,66 @@ gic: interrupt-controller@14900000 { interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + sdhi0: mmc@15c00000 { + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c00000 0 0x10000>; + interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa7>; + power-domains = <&cpg>; + status = "disabled"; + + vqmmc_sdhi0: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi1: mmc@15c10000 { + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c10000 0 0x10000>; + interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, + <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa8>; + power-domains = <&cpg>; + status = "disabled"; + + vqmmc_sdhi1: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi2: mmc@15c20000 { + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c20000 0 0x10000>; + interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, + <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa9>; + power-domains = <&cpg>; + status = "disabled"; + + vqmmc_sdhi2: vqmmc-regulator { + regulator-name = "SDHI2-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; }; timer {
Add SDHI0-SDHI2 nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2: * Status of internal regulator is disabled in the SoC .dtsi. Override the status in the board DTS when needed. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+)