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[v4,1/9] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG

Message ID 20250210184910.161780-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Under Review
Delegated to: Geert Uytterhoeven
Headers show
Series Add support to configure CPG block for watchdog on RZ/V2H(P) and RZ/G3E SoCs | expand

Commit Message

Lad, Prabhakar Feb. 10, 2025, 6:49 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
(`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
trigger a system reset in response to specific error conditions, while the
`CPG_ERROR_RSTm` registers store the error interrupt factors that caused
the system reset. These registers can be used by various IP blocks as
needed.

For example, in `CPG_ERRORRST_SEL2`, setting `BIT(1)` enables the WDT1 to
issue a system reset upon a watchdog timer underflow. Similarly, `BIT(1)`
in `CPG_ERROR_RST2` indicates whether the system reset was caused by a
WDT1 underflow. This functionality allows the watchdog driver to configure
the CPG_ERRORRST_SEL2 register and determine whether the system booted due
to a `Power-on Reset` or a `Watchdog Reset`.

Add the `syscon` compatible property to the RZ/V2H(P) and RZ/G3E CPG
blocks, enabling drivers to access the `CPG_ERRORRST_SELm` and
`CPG_ERROR_RSTm` registers as needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- Updated commit meessage

v2->v3
- No change

v1->v2
- No change
---
 .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml   | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index c3fe76abd549..f42d79e73e70 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -17,9 +17,11 @@  description:
 
 properties:
   compatible:
-    enum:
-      - renesas,r9a09g047-cpg # RZ/G3E
-      - renesas,r9a09g057-cpg # RZ/V2H
+    items:
+      - enum:
+          - renesas,r9a09g047-cpg # RZ/G3E
+          - renesas,r9a09g057-cpg # RZ/V2H
+      - const: syscon
 
   reg:
     maxItems: 1
@@ -73,7 +75,7 @@  additionalProperties: false
 examples:
   - |
     clock-controller@10420000 {
-        compatible = "renesas,r9a09g057-cpg";
+        compatible = "renesas,r9a09g057-cpg", "syscon";
         reg = <0x10420000 0x10000>;
         clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
         clock-names = "audio_extal", "rtxin", "qextal";