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Mon, 10 Feb 2025 10:49:33 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:b833:1deb:a929:b461]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439452533ecsm22911525e9.0.2025.02.10.10.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 10:49:32 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 5/9] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property Date: Mon, 10 Feb 2025 18:49:06 +0000 Message-ID: <20250210184910.161780-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250210184910.161780-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250210184910.161780-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers (`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to trigger a system reset in response to specific error conditions, while the `CPG_ERROR_RSTm` registers store the error interrupt factors that caused the system reset. For the watchdog IP to trigger a system reset on a watchdog timer underflow, the `CPG_ERRORRST_SEL2` and `CPG_ERROR_RST2` registers in the CPG block must be configured. For example, setting `BIT(1)` in `CPG_ERRORRST_SEL2` allows WDT1 to issue a system reset upon a watchdog timer underflow. Similarly, `BIT(1)` in `CPG_ERROR_RST2` indicates whether the system reset was caused by a WDT1 underflow. This functionality enables the watchdog driver to configure the `CPG_ERRORRST_SEL2` register and determine whether the system booted due to a `Power-on Reset` or a `Watchdog Reset`. To support this operation, add the `renesas,syscon-cpg-error-rst` property to the WDT node. This property maps to the `syscon` CPG node, allowing the watchdog driver to configure and retrieve the necessary reset information. Additionally, this property is marked as required for the RZ/V2H(P) and RZ/G3E SoC to ensure future compatibility and is explicitly disallowed for other SoCs. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring (Arm) --- Note, this change doesnt break any ABI, as the subsequent driver patch handles the case elegantly if the `syscon` node is missing to handle backward compatibility. v3->v4 - Updated commit message v2->v3 - No change v1->v2 - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst` - Updated commit message --- .../bindings/watchdog/renesas,wdt.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index 29ada89fdcdc..ca62ae8b1b0c 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -112,6 +112,19 @@ properties: timeout-sec: true + renesas,syscon-cpg-error-rst: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The first cell is a phandle to the SYSCON entry required to obtain + the current boot status. The second cell specifies the CPG_ERROR_RSTm + register offset within the SYSCON, and the third cell indicates the + bit within the CPG_ERROR_RSTm register. + items: + - items: + - description: Phandle to the CPG node + - description: The CPG_ERROR_RSTm register offset + - description: The bit within CPG_ERROR_RSTm register of interest + required: - compatible - reg @@ -182,7 +195,11 @@ allOf: properties: interrupts: false interrupt-names: false + required: + - renesas,syscon-cpg-error-rst else: + properties: + renesas,syscon-cpg-error-rst: false required: - interrupts