| Message ID | 20250315152708.328036-4-niklas.soderlund+renesas@ragnatech.se (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | rcar-isp: Prepare for ISP core support | expand |
Hi Niklas On Sat, Mar 15, 2025 at 04:27:04PM +0100, Niklas Söderlund wrote: > All ISP instances on V4H have both a channel select and core function > block, describe the core region in addition to the existing cs region. > > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> Thanks j > --- > arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 30 +++++++++++++++++------ > 1 file changed, 22 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi > index 1760720b7128..6dbf05a55935 100644 > --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi > @@ -2277,13 +2277,20 @@ du_out_dsi1: endpoint { > isp0: isp@fed00000 { > compatible = "renesas,r8a779g0-isp", > "renesas,rcar-gen4-isp"; > - reg = <0 0xfed00000 0 0x10000>; > - interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&cpg CPG_MOD 612>; > + reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>; > + reg-names = "cs", "core"; > + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "cs", "core"; > + clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>; > + clock-names = "cs", "core"; > power-domains = <&sysc R8A779G0_PD_A3ISP0>; > - resets = <&cpg 612>; > + resets = <&cpg 612>, <&cpg 16>; > + reset-names = "cs", "core"; > status = "disabled"; > > + renesas,vspx = <&vspx0>; > + > ports { > #address-cells = <1>; > #size-cells = <0>; > @@ -2361,13 +2368,20 @@ isp0vin07: endpoint { > isp1: isp@fed20000 { > compatible = "renesas,r8a779g0-isp", > "renesas,rcar-gen4-isp"; > - reg = <0 0xfed20000 0 0x10000>; > - interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>; > - clocks = <&cpg CPG_MOD 613>; > + reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>; > + reg-names = "cs", "core"; > + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "cs", "core"; > + clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>; > + clock-names = "cs", "core"; > power-domains = <&sysc R8A779G0_PD_A3ISP1>; > - resets = <&cpg 613>; > + resets = <&cpg 613>, <&cpg 17>; > + reset-names = "cs", "core"; > status = "disabled"; > > + renesas,vspx = <&vspx1>; > + > ports { > #address-cells = <1>; > #size-cells = <0>; > -- > 2.48.1 > >
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 1760720b7128..6dbf05a55935 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2277,13 +2277,20 @@ du_out_dsi1: endpoint { isp0: isp@fed00000 { compatible = "renesas,r8a779g0-isp", "renesas,rcar-gen4-isp"; - reg = <0 0xfed00000 0 0x10000>; - interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cpg CPG_MOD 612>; + reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>; + reg-names = "cs", "core"; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cs", "core"; + clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>; + clock-names = "cs", "core"; power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 612>; + resets = <&cpg 612>, <&cpg 16>; + reset-names = "cs", "core"; status = "disabled"; + renesas,vspx = <&vspx0>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -2361,13 +2368,20 @@ isp0vin07: endpoint { isp1: isp@fed20000 { compatible = "renesas,r8a779g0-isp", "renesas,rcar-gen4-isp"; - reg = <0 0xfed20000 0 0x10000>; - interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>; - clocks = <&cpg CPG_MOD 613>; + reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>; + reg-names = "cs", "core"; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cs", "core"; + clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>; + clock-names = "cs", "core"; power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 613>; + resets = <&cpg 613>, <&cpg 17>; + reset-names = "cs", "core"; status = "disabled"; + renesas,vspx = <&vspx1>; + ports { #address-cells = <1>; #size-cells = <0>;
All ISP instances on V4H have both a channel select and core function block, describe the core region in addition to the existing cs region. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 30 +++++++++++++++++------ 1 file changed, 22 insertions(+), 8 deletions(-)