From patchwork Thu Mar 20 09:10:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 14023571 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6925C21ADCC; Thu, 20 Mar 2025 09:12:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742461940; cv=none; b=lcu7EIUtjWvuulqVaIQb0CkZLs2YDM5ceqO92cBct1d0BdmH9qQx+66VRkqq7oD3WWq1SPbYmZlixNQbJvK3ov9I2tYAGpi/d1kEZ6mcF0X3q7qoMgTwu0s8aE9W9smRuW/5CKgmQ6+2RBDgfT95x3U3lvYizz5047wZwUfaFSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742461940; c=relaxed/simple; bh=aF+WjSE/9OhGGVMB7/9ZYjRflyzXObAKn/+EPq7vW+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FT7nwAzBlxNDGu+vQczjy+D2SWPIjGvDdmUHqQOxFGpSOrRbgQNq5lzEWV6cjo94uzQrupTelRUAJnEfufIciqPxS0pGwhFrx92Q/A3HeVCuTguu+5TcWn0THv4iBD7UyycZVymtuLrbcqDL2j00u+qP9kKx7eBtxY23E9O8sGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: BpcTdHdQRFm/Om6fS7cpug== X-CSE-MsgGUID: ostQLwWaSvaI+HvITUmtYg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 20 Mar 2025 18:12:17 +0900 Received: from localhost.localdomain (unknown [10.226.93.24]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 552334001B61; Thu, 20 Mar 2025 18:12:14 +0900 (JST) From: Biju Das To: Marc Kleine-Budde , Vincent Mailhol Cc: Biju Das , Wolfram Sang , Geert Uytterhoeven , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , linux-can@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 18/18] can: rcar_canfd: Add RZ/G3E support Date: Thu, 20 Mar 2025 09:10:49 +0000 Message-ID: <20250320091101.33637-19-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250320091101.33637-1-biju.das.jz@bp.renesas.com> References: <20250320091101.33637-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The CAN-FD IP found on the RZ/G3E SoC is similar to R-Car Gen4, but it has no external clock instead it has clk_ram, it has 6 channels and supports 20 interrupts. Add support for RZ/G3E CAN-FD driver. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v5->v6: * Collected tag * Updated r9a09g047_hw_info table. v4->v5: * Updated error description as "cannot get enabled ram clock" * Updated r9a09g047_hw_info table. v3->v4: * No change. v2->v3: * Replaced gen4_type entry with mask_table, shift_table, regs, ch_interface_mode and shared_can_reg. v1->v2: * No change. --- drivers/net/can/rcar/rcar_canfd.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c index 91f5649078c6..243eaf6c24c4 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -730,6 +730,24 @@ static const struct rcar_canfd_hw_info rzg2l_hw_info = { .multi_channel_irqs = 1, }; +static const struct rcar_canfd_hw_info r9a09g047_hw_info = { + .nom_bittiming = &rcar_canfd_gen4_nom_bittiming_const, + .data_bittiming = &rcar_canfd_gen4_data_bittiming_const, + .regs = rcar_gen4_regs, + .shift_table = rcar_gen4_shift_table, + .num_supported_rules = 512, + .rnc_stride = 2, + .rnc_field_width = 16, + .max_aflpn = 63, + .max_cftml = 31, + .max_channels = 6, + .postdiv = 1, + .multi_channel_irqs = 1, + .ch_interface_mode = 1, + .shared_can_regs = 1, + .only_internal_clks = 1, +}; + /* Helper functions */ static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg) { @@ -1963,6 +1981,7 @@ static int rcar_canfd_probe(struct platform_device *pdev) u32 rule_entry = 0; bool fdmode = true; /* CAN FD only mode - default */ char name[9] = "channelX"; + struct clk *clk_ram; int i; info = of_device_get_match_data(dev); @@ -2052,6 +2071,11 @@ static int rcar_canfd_probe(struct platform_device *pdev) gpriv->extclk = !gpriv->info->only_internal_clks; } + clk_ram = devm_clk_get_optional_enabled(dev, "ram_clk"); + if (IS_ERR(clk_ram)) + return dev_err_probe(dev, PTR_ERR(clk_ram), + "cannot get enabled ram clock\n"); + addr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(addr)) { err = PTR_ERR(addr); @@ -2214,6 +2238,7 @@ static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend, static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = { { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info }, + { .compatible = "renesas,r9a09g047-canfd", .data = &r9a09g047_hw_info }, { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info }, { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info }, { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },