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([82.78.167.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fdbcfaasm120146525e9.35.2025.03.24.06.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Mar 2025 06:57:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH v3 3/4] arm64: dts: renesas: r9a08g045: Add TSU node Date: Mon, 24 Mar 2025 15:57:00 +0200 Message-ID: <20250324135701.179827-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> References: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. The temperature reported by the TSU can only be read through channel 8 of the ADC. Therefore, enable the ADC by default. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected Geert's tag - adjusted the trip points temperature as suggested in the review process - added cpu_alert1 passive trip point as suggested in the review process; along with it changed the trip point nodes and label names Hi, Geert, I kept your Rb tag. Please let me know if it should be dropped. Thank you, Claudiu arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 49 ++++++++++++++++++- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 -- 2 files changed, 48 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0364f89776e6..3f56fff7d9b0 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -233,7 +233,6 @@ adc: adc@10058000 { #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - status = "disabled"; channel@0 { reg = <0>; @@ -272,6 +271,17 @@ channel@8 { }; }; + tsu: thermal@10059000 { + compatible = "renesas,r9a08g045-tsu"; + reg = <0 0x10059000 0 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets = <&cpg R9A08G045_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + io-channels = <&adc 8>; + io-channel-names = "tsu"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; @@ -717,6 +727,43 @@ timer { "hyp-virt"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu>; + sustainable-power = <423>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + cpu_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_alert1: trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vbattb_xtal: vbattb-xtal { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 39845faec894..6f25ab617982 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -84,10 +84,6 @@ x3_clk: x3-clock { }; }; -&adc { - status = "okay"; -}; - #if SW_CONFIG3 == SW_ON ð0 { pinctrl-0 = <ð0_pins>;