Message ID | 20250325160904.2688858-8-thierry.bultel.yh@bp.renesas.com (mailing list archive) |
---|---|
State | New |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add initial support for Renesas RZ/T2H SoC | expand |
On Tue, 25 Mar 2025 at 17:09, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote: > The comment was correct when it was added, at that time RZ/T1 was > the only SoC in the RZ/T line. Since then, further SoCs have been > added with RZ/T names which do not use the same SCIFA register > layout and so the comment is now misleading. > > So we update the comment to explicitly reference only RZ/T1 SoCs. > > Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 1c8480d0338e..d7a060033a89 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -310,7 +310,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { }, /* - * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. + * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1. * It looks like a normal SCIF with FIFO data, but with a * compressed address space. Also, the break out of interrupts * are different: ERI/BRI, RXI, TXI, TEI, DRI.