| Message ID | 20250328153134.2881-9-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | ARM: dts: renesas: r9a06g032-rzn1d400-db: enable I2C infrastructure | expand |
On 3/28/25 6:31 PM, Wolfram Sang wrote: > Schematics mention a 24cs64 on the bus, but I definitely have only a > 24c64. So, it is only mentioned as a comment. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > .../dts/renesas/r9a06g032-rzn1d400-db.dts | 44 +++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts > index 31cdca3e623c..d50a1d91e968 100644 > --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts > +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts > @@ -57,6 +57,44 @@ fixed-link { > }; > }; > > +&i2c2 { > + pinctrl-0 = <&pins_i2c2>; > + pinctrl-names = "default"; > + status = "okay"; > + clock-frequency = <400000>; [...]> + /* Some revisions may have a 24cs64 at address 0x58 */ > + eeprom@50 { So 0x58 or 0x50? > + compatible = "atmel,24c64"; > + pagesize = <32>; > + reg = <0x50>; > + }; > +}; > + > &mii_conv4 { > renesas,miic-input = <MIIC_SWITCH_PORTB>; > status = "okay"; [...] MBR, Sergey
> [...]> + /* Some revisions may have a 24cs64 at address 0x58 */ > > + eeprom@50 { > > So 0x58 or 0x50? The eeprom is at 0x50, always. The serial ID (the cs-part) is at 0x58. This is always the case for cs-eeproms, see their existing usage in DT.
diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index 31cdca3e623c..d50a1d91e968 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -57,6 +57,44 @@ fixed-link { }; }; +&i2c2 { + pinctrl-0 = <&pins_i2c2>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <400000>; + + pca9698: gpio@20 { + compatible = "nxp,pca9698"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + /* configure the analog switch to let i2c2 access the eeprom */ + max4662-in1-hog { + gpio-hog; + gpios = <16 0>; + output-high; + }; + max4662-in2-hog { + gpio-hog; + gpios = <17 0>; + output-low; + }; + max4662-in3-hog { + gpio-hog; + gpios = <18 0>; + output-low; + }; + }; + + /* Some revisions may have a 24cs64 at address 0x58 */ + eeprom@50 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x50>; + }; +}; + &mii_conv4 { renesas,miic-input = <MIIC_SWITCH_PORTB>; status = "okay"; @@ -114,6 +152,12 @@ pins_eth4: pins_eth4 { bias-disable; }; + pins_i2c2: pins_i2c2 { + pinmux = <RZN1_PINMUX(115, RZN1_FUNC_I2C)>, + <RZN1_PINMUX(116, RZN1_FUNC_I2C)>; + drive-strength = <12>; + }; + pins_mdio1: pins_mdio1 { pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>, <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
Schematics mention a 24cs64 on the bus, but I definitely have only a 24c64. So, it is only mentioned as a comment. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- .../dts/renesas/r9a06g032-rzn1d400-db.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+)