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Fri, 28 Mar 2025 13:01:25 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:b400:d08:873:badd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d8fcceaaasm37930955e9.18.2025.03.28.13.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 13:01:24 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/6] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation Date: Fri, 28 Mar 2025 20:01:01 +0000 Message-ID: <20250328200105.176129-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Update the clock enable/disable logic to follow the latest hardware manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to confirm the clock state. According to the manual, enabling a clock requires setting the CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON bit. Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and confirming the clock has stopped via the CPG_CLK_MON bit. Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then validate CLK_ON for a more accurate clock status evaluation. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 817a39a8b852..dec97f731e3a 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -576,11 +576,14 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) if (clock->mon_index >= 0) { offset = GET_CLK_MON_OFFSET(clock->mon_index); bitmask = BIT(clock->mon_bit); - } else { - offset = GET_CLK_ON_OFFSET(clock->on_index); - bitmask = BIT(clock->on_bit); + + if (!(readl(priv->base + offset) & bitmask)) + return 0; } + offset = GET_CLK_ON_OFFSET(clock->on_index); + bitmask = BIT(clock->on_bit); + return readl(priv->base + offset) & bitmask; }