From patchwork Wed Jun 8 21:04:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9165687 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E616260832 for ; Wed, 8 Jun 2016 21:04:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D6CC624151 for ; Wed, 8 Jun 2016 21:04:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C9C8028047; Wed, 8 Jun 2016 21:04:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC51624151 for ; Wed, 8 Jun 2016 21:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423877AbcFHVEs (ORCPT ); Wed, 8 Jun 2016 17:04:48 -0400 Received: from mail-lf0-f54.google.com ([209.85.215.54]:36069 "EHLO mail-lf0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423166AbcFHVEs (ORCPT ); Wed, 8 Jun 2016 17:04:48 -0400 Received: by mail-lf0-f54.google.com with SMTP id j5so13838985lfb.3 for ; Wed, 08 Jun 2016 14:04:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:organization:user-agent:in-reply-to :references:mime-version:content-transfer-encoding; bh=CzpaD7c9XGOHOV3Z+QDK7lHS6deG01Pt0wsJCPw5QIU=; b=M1Tb5gM1hncVoyOA0r7p75SepJaZKcfkC9loZysG6+yQVuub5O6MV0t74vbhEx3NQA cJNC4nsIXyoYkOGS4Fw7ToHNNwm8fAFossder2I5wrDsXTdUsmBuBPLP7Qkdz88ttYrs 8wc8Z9XfQpryhgdAB6P6sYsj/uiowK/wS9QzJXO60sGcDYTMhb1DoOmxNvahma9B2jNz E5Wj2Y67ITRUQ2kZ1z2QziXpP/uu68sDNVvP/zuxnGMXkgai3MeM9WlOGS9SmkpWW3EV nwfJ/bsOnXM0f4B6xUjcYHnUhP49F4GVVnkuuAPBKsMlPggNTMA1DovLNe0KE3plMdkw 8aHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding; bh=CzpaD7c9XGOHOV3Z+QDK7lHS6deG01Pt0wsJCPw5QIU=; b=LrA6qirvscZpqRF7blUvXxprmu65FpbEbUqZ3BL5X+iAW+dVO6GStR4FiD5TFkeVaz rS9xsCMo6kSA/F/rvbq3UnA19I3LRZa2bM/sD3wKs+cF4GT37ewaH6aB0aDBVCemaoWD Ne3cdWrs035zZf8HE5blxdzN995VbOnx1B3S184tImk+KZotAQbSDjARCB+PLNGuHvHj bYwNm5ivLxPmTNczn8JMrHcTLb1g063k6ByCYGX9lRm9kM80pj+BgB2QU3mfRAfj6qhW wdh4rqdOh6k7ZkNeTJAEG43/A+i/FEH865nZ4lRIFf7Bp4H5iuER43Jd5ucF4lzORE8y 1XZQ== X-Gm-Message-State: ALyK8tImy8LjXTZC28xqW3vqujBoduAFLX4wOhcE7QE1v4neFpeUmX4D4QELYqXjrUXgpA== X-Received: by 10.25.150.75 with SMTP id y72mr311868lfd.92.1465419885963; Wed, 08 Jun 2016 14:04:45 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.85.233]) by smtp.gmail.com with ESMTPSA id n7sm106978lfb.31.2016.06.08.14.04.44 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 08 Jun 2016 14:04:45 -0700 (PDT) From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devicetree@vger.kernel.org Subject: [PATCH v3 01/12] ARM: shmobile: r8a7792: add clock index macros Date: Thu, 09 Jun 2016 00:04:43 +0300 Message-ID: <2256036.Aah0Fxjv7E@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.4.11-200.fc22.x86_64; KDE/4.14.17; x86_64; ; ) In-Reply-To: <12536856.AsKMEpuejQ@wasted.cogentembedded.com> References: <12536856.AsKMEpuejQ@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add macros usable by the device tree sources to reference the R8A7792 clocks by index. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 2: - removed the SDH, SD0, and SD1 clocks; - added RCAN and ADSP clock indeces; - fixed SYS-DMAC0/1 clock indeces. include/dt-bindings/clock/r8a7792-clock.h | 103 ++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) Index: renesas/include/dt-bindings/clock/r8a7792-clock.h =================================================================== --- /dev/null +++ renesas/include/dt-bindings/clock/r8a7792-clock.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ +#define __DT_BINDINGS_CLOCK_R8A7792_H__ + +/* CPG */ +#define R8A7792_CLK_MAIN 0 +#define R8A7792_CLK_PLL0 1 +#define R8A7792_CLK_PLL1 2 +#define R8A7792_CLK_PLL3 3 +#define R8A7792_CLK_LB 4 +#define R8A7792_CLK_QSPI 5 +#define R8A7792_CLK_Z 6 +#define R8A7792_CLK_RCAN 7 +#define R8A7792_CLK_ADSP 8 + +/* MSTP0 */ +#define R8A7792_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7792_CLK_TMU1 11 +#define R8A7792_CLK_TMU3 21 +#define R8A7792_CLK_TMU2 22 +#define R8A7792_CLK_CMT0 24 +#define R8A7792_CLK_TMU0 25 +#define R8A7792_CLK_VSP1DU1 27 +#define R8A7792_CLK_VSP1DU0 28 +#define R8A7792_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A7792_CLK_MSIOF1 8 +#define R8A7792_CLK_SYS_DMAC1 18 +#define R8A7792_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7792_CLK_TPU0 4 +#define R8A7792_CLK_SDHI0 14 +#define R8A7792_CLK_CMT1 29 + +/* MSTP4 */ +#define R8A7792_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7792_CLK_AUDIO_DMAC0 2 +#define R8A7792_CLK_THERMAL 22 +#define R8A7792_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7792_CLK_HSCIF1 16 +#define R8A7792_CLK_HSCIF0 17 +#define R8A7792_CLK_SCIF3 18 +#define R8A7792_CLK_SCIF2 19 +#define R8A7792_CLK_SCIF1 20 +#define R8A7792_CLK_SCIF0 21 +#define R8A7792_CLK_DU1 23 +#define R8A7792_CLK_DU0 24 + +/* MSTP8 */ +#define R8A7792_CLK_VIN5 4 +#define R8A7792_CLK_VIN4 5 +#define R8A7792_CLK_VIN3 8 +#define R8A7792_CLK_VIN2 9 +#define R8A7792_CLK_VIN1 10 +#define R8A7792_CLK_VIN0 11 +#define R8A7792_CLK_ETHERAVB 12 + +/* MSTP9 */ +#define R8A7792_CLK_GPIO7 4 +#define R8A7792_CLK_GPIO6 5 +#define R8A7792_CLK_GPIO5 7 +#define R8A7792_CLK_GPIO4 8 +#define R8A7792_CLK_GPIO3 9 +#define R8A7792_CLK_GPIO2 10 +#define R8A7792_CLK_GPIO1 11 +#define R8A7792_CLK_GPIO0 12 +#define R8A7792_CLK_GPIO11 13 +#define R8A7792_CLK_GPIO10 14 +#define R8A7792_CLK_CAN1 15 +#define R8A7792_CLK_CAN0 16 +#define R8A7792_CLK_QSPI_MOD 17 +#define R8A7792_CLK_GPIO9 19 +#define R8A7792_CLK_GPIO8 21 +#define R8A7792_CLK_I2C5 25 +#define R8A7792_CLK_IICDVFS 26 +#define R8A7792_CLK_I2C4 27 +#define R8A7792_CLK_I2C3 28 +#define R8A7792_CLK_I2C2 29 +#define R8A7792_CLK_I2C1 30 +#define R8A7792_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7792_CLK_SSI_ALL 5 +#define R8A7792_CLK_SSI4 11 +#define R8A7792_CLK_SSI3 12 + +#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */