Message ID | 50de037c-7560-c261-f96a-f86065674c9b@cogentembedded.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 116a12f7d6c00e1e477aaec9e486cd510fa1895c |
Delegated to: | Simon Horman |
Headers | show |
On Thu, May 10, 2018 at 09:12:30PM +0300, Sergei Shtylyov wrote: > Add the initial device tree for the V3H Starter Kit board. > The board has 1 debug serial port (SCIF0); include support for it, > so that the serial console can work. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> This looks fine but I will wait to see if there are other reviews before applying. Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
On Sun, May 13, 2018 at 10:07:04AM +0200, Simon Horman wrote: > On Thu, May 10, 2018 at 09:12:30PM +0300, Sergei Shtylyov wrote: > > Add the initial device tree for the V3H Starter Kit board. > > The board has 1 debug serial port (SCIF0); include support for it, > > so that the serial console can work. > > > > Based on the original (and large) patch by Vladimir Barinov. > > > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > This looks fine but I will wait to see if there are other reviews before > applying. > > Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Applied
On Thu, May 10, 2018 at 8:12 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the initial device tree for the V3H Starter Kit board. > The board has 1 debug serial port (SCIF0); include support for it, > so that the serial console can work. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> FTR: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- /dev/null > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts > +&pfc { > + scif0_pins: scif0 { > + groups = "scif0_data"; > + function = "scif0"; > + }; JFYI, hscif0 can be routed to the same pins, if higher performance is needed. Gr{oetje,eeting}s, Geert
Index: renesas/arch/arm64/boot/dts/renesas/Makefile =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/Makefile +++ renesas/arch/arm64/boot/dts/renesas/Makefile @@ -9,6 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb -dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts =================================================================== --- /dev/null +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the V3H Starter Kit board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" + +/ { + model = "Renesas V3H Starter Kit board"; + compatible = "renesas,v3hsk", "renesas,r8a77980"; + + aliases { + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +};