| Message ID | 513dd4ea-7309-d2a3-7940-b14bc1836c31@de.bosch.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
> What's the status of SDHI support in mainline and/or renesas-drivers > (renesas-drivers-2017-08-16-v4.13-rc5)? I use it daily here, even with SDR104 enabled. > sdhci-pltfm: SDHCI platform and OF driver helper Wrong driver? We have SDHI not SDHCI.
Hi Dirk, On Thu, Aug 17, 2017 at 9:23 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote: > since ages I tried recent mainline (v4.13-rc5) on a custom r8a7795 board. R-Car H3 ES1.x or ES2.0? > I tried with the attachment and picked some patches from > renesas-drivers-2017-08-16-v4.13-rc5 [1] but it doesn't look like any SD > card / eMMC is detected at all [2]. That patch is for ES2.0. There are indeed no SDHI pins in the upstream pinctrl driver for ES2.0 yet. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 17.08.2017 09:33, Geert Uytterhoeven wrote: > Hi Dirk, > > On Thu, Aug 17, 2017 at 9:23 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote: >> since ages I tried recent mainline (v4.13-rc5) on a custom r8a7795 board. > > R-Car H3 ES1.x or ES2.0? ES2.0 >> I tried with the attachment and picked some patches from >> renesas-drivers-2017-08-16-v4.13-rc5 [1] but it doesn't look like any SD >> card / eMMC is detected at all [2]. > > That patch is for ES2.0. There are indeed no SDHI pins in the upstream pinctrl > driver for ES2.0 yet. So its fine to send the attached patch for integration? Best regards Dirk
Hi Dirk, On Thu, Aug 17, 2017 at 9:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote: > On 17.08.2017 09:33, Geert Uytterhoeven wrote: >> On Thu, Aug 17, 2017 at 9:23 AM, Dirk Behme <dirk.behme@de.bosch.com> >> wrote: >>> since ages I tried recent mainline (v4.13-rc5) on a custom r8a7795 board. >> >> R-Car H3 ES1.x or ES2.0? > > ES2.0 > >>> I tried with the attachment and picked some patches from >>> renesas-drivers-2017-08-16-v4.13-rc5 [1] but it doesn't look like any SD >>> card / eMMC is detected at all [2]. >> >> That patch is for ES2.0. There are indeed no SDHI pins in the upstream >> pinctrl >> driver for ES2.0 yet. > > So its fine to send the attached patch for integration? Yes, iff it works. But you claim it doesn't? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 17.08.2017 09:48, Geert Uytterhoeven wrote: > Hi Dirk, > > On Thu, Aug 17, 2017 at 9:44 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote: >> On 17.08.2017 09:33, Geert Uytterhoeven wrote: >>> On Thu, Aug 17, 2017 at 9:23 AM, Dirk Behme <dirk.behme@de.bosch.com> >>> wrote: >>>> since ages I tried recent mainline (v4.13-rc5) on a custom r8a7795 board. >>> >>> R-Car H3 ES1.x or ES2.0? >> >> ES2.0 >> >>>> I tried with the attachment and picked some patches from >>>> renesas-drivers-2017-08-16-v4.13-rc5 [1] but it doesn't look like any SD >>>> card / eMMC is detected at all [2]. >>> >>> That patch is for ES2.0. There are indeed no SDHI pins in the upstream >>> pinctrl >>> driver for ES2.0 yet. >> >> So its fine to send the attached patch for integration? > > Yes, iff it works. But you claim it doesn't? Well, at least it removes the error messages regarding pinctrl [1]. Yes, as mentioned, if in the end SD / eMMC work I can't say, yet. Best regards Dirk [1] sh-pfc e6060000.pin-controller: function 'sdhi0' not supported sh-pfc e6060000.pin-controller: invalid function sdhi0 in map table sh-pfc e6060000.pin-controller: does not have pin group sdhi0_data4 sh-pfc e6060000.pin-controller: could not map group config for "sdhi0_data4" sh-pfc e6060000.pin-controller: function 'sdhi0' not supported sh-pfc e6060000.pin-controller: invalid function sdhi0 in map table sh-pfc e6060000.pin-controller: does not have pin group sdhi0_ctrl sh-pfc e6060000.pin-controller: could not map group config for "sdhi0_ctrl" sh-pfc e6060000.pin-controller: function 'sdhi0' not supported sh-pfc e6060000.pin-controller: invalid function sdhi0 in map table sh-pfc e6060000.pin-controller: does not have pin group sdhi0_data4 sh-pfc e6060000.pin-controller: could not map group config for "sdhi0_data4" sh-pfc e6060000.pin-controller: function 'sdhi0' not supported sh-pfc e6060000.pin-controller: invalid function sdhi0 in map table sh-pfc e6060000.pin-controller: does not have pin group sdhi0_ctrl sh-pfc e6060000.pin-controller: could not map group config for "sdhi0_ctrl" sh_mobile_sdhi: probe of ee100000.sd failed with error -22
On 17.08.2017 09:29, Wolfram Sang wrote: > >> What's the status of SDHI support in mainline and/or renesas-drivers >> (renesas-drivers-2017-08-16-v4.13-rc5)? > > I use it daily here, even with SDR104 enabled. On ES2.0? I wonder how if not even the pinmux is there ;) >> sdhci-pltfm: SDHCI platform and OF driver helper > > Wrong driver? We have SDHI not SDHCI. Changing the config a little I have --cut -- CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_PWRSEQ_EMMC is not set # CONFIG_PWRSEQ_SIMPLE is not set CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=8 # CONFIG_SDIO_UART is not set # CONFIG_MMC_TEST is not set # # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_ARMMMCI is not set # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_TIFM_SD is not set # CONFIG_MMC_SPI is not set CONFIG_MMC_TMIO_CORE=y CONFIG_MMC_SDHI=y CONFIG_MMC_SDHI_SYS_DMAC=y CONFIG_MMC_SDHI_INTERNAL_DMAC=y -- cut -- now. As SDHCI is disabled, now, I don't get anything SD/MMC related in the boot log any more. Not even an error message. Hmm ... The device tree has [1]. Best regards Dirk [1] &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; pinctrl-names = "default"; vmmc-supply = <®_3p3v>; non-removable; /* Workaround due to CD on CPLD */ bus-width = <4>; no-1-8-v; status = "okay"; }; &sdhi3 { /* used for on-board 8bit eMMC */ pinctrl-0 = <&sdhi3_pins>; pinctrl-1 = <&sdhi3_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_1p8v>; mmc-hs400-1_8v; bus-width = <8>; non-removable; status = "okay"; };
> > > What's the status of SDHI support in mainline and/or renesas-drivers > > > (renesas-drivers-2017-08-16-v4.13-rc5)? > > > > I use it daily here, even with SDR104 enabled. > > On ES2.0? I wonder how if not even the pinmux is there ;) Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I will try to test your patch on my Salvator-XS board today. > mmc-hs400-1_8v; We only have HS200 support upstream. Other than that, I don't see any problems in the DTS snipplet.
On 18.08.2017 11:00, Wolfram Sang wrote: > >>>> What's the status of SDHI support in mainline and/or renesas-drivers >>>> (renesas-drivers-2017-08-16-v4.13-rc5)? >>> >>> I use it daily here, even with SDR104 enabled. >> >> On ES2.0? I wonder how if not even the pinmux is there ;) > > Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I > will try to test your patch on my Salvator-XS board today. Ok, thanks :) >> mmc-hs400-1_8v; > > We only have HS200 support upstream. Other than that, I don't see any > problems in the DTS snipplet. But even if this is wrong, at least some error messages should be given, no? As mentioned, there was nothing. So I'd assume a more basic issue, like missing clock or compatible or similar. Best regards Dirk
> > > mmc-hs400-1_8v; > > > > We only have HS200 support upstream. Other than that, I don't see any > > problems in the DTS snipplet. > > But even if this is wrong, at least some error messages should be given, no? Yes, this was additional information. It is not the cause for your problem. > As mentioned, there was nothing. So I'd assume a more basic issue, like > missing clock or compatible or similar. Yes, something like that. Although, SDHI print prints out on some errors like missing clocks (or success) during probe. Can you try disabling CONFIG_MMC_SDHI_SYS_DMAC=y? It shouldn't matter, but maybe it does. Thanks, Wolfram
Hi Dirk, > > Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I > > will try to test your patch on my Salvator-XS board today. > > Ok, thanks :) Your patch on top of v4.13-rc5 makes SDHI work on my Salvator-XS with a H3 ES2.0. It detects the eMMC and I can mount SD cards on both slots and checksum large files. Enabling SDHI on ES2.0 in upstream is scheduled for next week. Regards, Wolfram
On 21.08.2017 10:18, Wolfram Sang wrote: > Hi Dirk, > >>> Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I >>> will try to test your patch on my Salvator-XS board today. >> >> Ok, thanks :) > > Your patch on top of v4.13-rc5 makes SDHI work on my Salvator-XS with a Please feel free to forward it to the correct channels for merge, then. > H3 ES2.0. It detects the eMMC and I can mount SD cards on both slots and > checksum large files. Hmm, sounds like I have to search on my custom board why there is not output at all, then :( Anyway, many thanks for testing! Best regards Dirk
On 21.08.2017 10:24, Dirk Behme wrote: > On 21.08.2017 10:18, Wolfram Sang wrote: >> Hi Dirk, >> >>>> Ah, ES2.0. That's the missing information. Yup, is on the todo-list. I >>>> will try to test your patch on my Salvator-XS board today. >>> >>> Ok, thanks :) >> >> Your patch on top of v4.13-rc5 makes SDHI work on my Salvator-XS with a > > > Please feel free to forward it to the correct channels for merge, then. > > >> H3 ES2.0. It detects the eMMC and I can mount SD cards on both slots and >> checksum large files. > > > Hmm, sounds like I have to search on my custom board why there is not > output at all, then :( It works, now :) Just for the logs: While creating the defconfig for testing v4.13-rc5 somehow CONFIG_GPIOLIB=y CONFIG_GPIO_RCAR=y was dropped. Without GPIO support the statement of_get_fixed_voltage_config(...) { ... config->gpio = of_get_named_gpio(np, "gpio", 0); if ((config->gpio < 0) && (config->gpio != -ENOENT)) { failed, resulting in failing regulator support. Without regulator support tmio_mmc_init_ocr() fails (silently!). And with this the whole RCar3 SDHI, without any error message. Enabling GPIO does fix the issue. Many thanks for your help! Dirk P.S.: Will try to send the pin mux patch tomorrow.
> It works, now :) Great! > tmio_mmc_init_ocr() > > fails (silently!). And with this the whole RCar3 SDHI, without any error > message. I'll check next week about an error message there. > Many thanks for your help! You're welcome. If you want, you can even test SDR104 by applying this patch: [RFT] arm64: dts: renesas: salvator-common: enable SDR104 for SD cards It works fine here for SD cards. My SDIO card makes problems, but that might be the line length is just too long. We are currently evaluating that. So, testing SDR104 on various boards would be very helpful! > P.S.: Will try to send the pin mux patch tomorrow. Thanks, I'll have a look at it next week then, too.
On 21.08.2017 15:47, Wolfram Sang wrote: > >> It works, now :) > > Great! > >> tmio_mmc_init_ocr() >> >> fails (silently!). And with this the whole RCar3 SDHI, without any error >> message. > > I'll check next week about an error message there. > >> Many thanks for your help! > > You're welcome. If you want, you can even test SDR104 by applying this > patch: > > [RFT] arm64: dts: renesas: salvator-common: enable SDR104 for SD cards > > It works fine here for SD cards. My SDIO card makes problems, but that > might be the line length is just too long. We are currently evaluating > that. So, testing SDR104 on various boards would be very helpful! I'm not an expert on this, does SDR104 need 1.8V? To my understanding, sd-uhs-sdr50 is the max speed for 3.3V? I ask because on my custom board the hardware guys gave us 3.3V, only, for the SD slot :( >> P.S.: Will try to send the pin mux patch tomorrow. > > Thanks, I'll have a look at it next week then, too. Patch sent. Best regards Dirk
> I'm not an expert on this, does SDR104 need 1.8V? > > To my understanding, sd-uhs-sdr50 is the max speed for 3.3V? Nope, everything with SDR* needs 1.8V. So, classic "highspeed" is the maximum for your slot. > I ask because on my custom board the hardware guys gave us 3.3V, only, for > the SD slot :( Pity, in deed.
On 22.08.2017 08:56, Wolfram Sang wrote: > >> I'm not an expert on this, does SDR104 need 1.8V? >> >> To my understanding, sd-uhs-sdr50 is the max speed for 3.3V? > > Nope, everything with SDR* needs 1.8V. So, classic "highspeed" is the > maximum for your slot. > >> I ask because on my custom board the hardware guys gave us 3.3V, only, for >> the SD slot :( > > Pity, in deed. Yes, indeed :( Btw, whats about HS400 support for the eMMC? As the eMMC is often the 'mass storage' device for the rootfs, the eMMC performance will have a direct influence to the overall system performance. Dirk
> Btw, whats about HS400 support for the eMMC? As the eMMC is often the 'mass > storage' device for the rootfs, the eMMC performance will have a direct > influence to the overall system performance. Sure, I know. We finally have Gen3 SDHI DMA upstream and SDR104 seems to be stable as well (we are still testing corner cases, though). HS400 would obviously be next.
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 1656295af2b0..60def0dc0761 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -2040,6 +2040,213 @@ static const unsigned int scif5_clk_b_mux[] = { SCK5_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi2_data8_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, + SD2_DAT4_MARK, SD2_DAT5_MARK, + SD2_DAT6_MARK, SD2_DAT7_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_a_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int sdhi2_cd_a_mux[] = { + SD2_CD_A_MARK, +}; +static const unsigned int sdhi2_cd_b_pins[] = { + /* CD */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int sdhi2_cd_b_mux[] = { + SD2_CD_B_MARK, +}; +static const unsigned int sdhi2_wp_a_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int sdhi2_wp_a_mux[] = { + SD2_WP_A_MARK, +}; +static const unsigned int sdhi2_wp_b_pins[] = { + /* WP */ + RCAR_GP_PIN(5, 11), +}; +static const unsigned int sdhi2_wp_b_mux[] = { + SD2_WP_B_MARK, +}; +static const unsigned int sdhi2_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int sdhi2_ds_mux[] = { + SD2_DS_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 9), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; + /* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { /* SCIF_CLK */ @@ -2117,6 +2324,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), }; static const char * const avb_groups[] = { @@ -2227,6 +2460,44 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_data8", + "sdhi2_ctrl", + "sdhi2_cd_a", + "sdhi2_wp_a", + "sdhi2_cd_b", + "sdhi2_wp_b", + "sdhi2_ds", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du), @@ -2244,6 +2515,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Hi, since ages I tried recent mainline (v4.13-rc5) on a custom r8a7795 board. What's the status of SDHI support in mainline and/or renesas-drivers (renesas-drivers-2017-08-16-v4.13-rc5)? I tried with the attachment and picked some patches from renesas-drivers-2017-08-16-v4.13-rc5 [1] but it doesn't look like any SD card / eMMC is detected at all [2]. In contrast to this, using recent 4.9 based Renesas BSP works quite well with both, SD card and eMMC. Anything I missed or should pick additionally? Best regards Dirk [1] a3e6e7e64191 mmc: renesas-sdhi: provide a whitelist for Gen3 SoC ES versions bc3db4f2fd33 mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit 2fcc3bd20347 mmc: tmio: don't wait on R-Car2+ when handling the clock c67c49abb8cc mmc: tmio: no magic values when enabling DMA b22af30b538b mmc: tmio: add references to bit defines in the header 9189f77a81fe mmc: tmio: remove obsolete TMIO_BBS 9493a1c932e5 mmc: tmio: fix CMD12 (STOP) handling 52c175e556f2 mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC b713254ddb3e mmc: tmio, renesas-sdhi: add dataend to DMA ops 12c02bec700b mmc: tmio, renesas-sdhi: add max_{segs, blk_count} to tmio_mmc_data ae0ba4472354 pinctrl: sh-pfc: r8a7795: Add SDHIx support ef954844c7ac Linux 4.13-rc5 [2] ... rcar_gen3_thermal e6198000.thermal: TSC2: Loaded 1 trip points sdhci: Secure Digital Host Controller Interface driver sdhci: Copyright(c) Pierre Ossman sdhci-pltfm: SDHCI platform and OF driver helper hidraw: raw HID events driver (C) Jiri Kosina NET: Registered protocol family 17 ... From ae0ba44723548f835824ad8f2f96dd971cfedb0f Mon Sep 17 00:00:00 2001 From: Dirk Behme <dirk.behme@de.bosch.com> Date: Thu, 17 Aug 2017 08:02:14 +0200 Subject: [PATCH] pinctrl: sh-pfc: r8a7795: Add SDHIx support Taken from the Renesas BSP https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/tree/drivers/pinctrl/sh-pfc/pfc-r8a7795.c FIXME: Clarify why this isn't mainline and mainline it. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 275 +++++++++++++++++++++++++++++++++++ 1 file changed, 275 insertions(+)