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[07/31] ARM: dts: r8a7745: Remove unit-address and reg from integrated cache

Message ID 51c00a9f730dd27da23e9dec593c22c0f9f5a1b1.1489999062.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit 51c00a9f730dd27da23e9dec593c22c0f9f5a1b1
Delegated to: Simon Horman
Headers show

Commit Message

Simon Horman March 20, 2017, 8:57 a.m. UTC 
From: Geert Uytterhoeven <geert+renesas@glider.be>

The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.

Fixes: c95360247bdd67d3 ("ARM: dts: r8a7745: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7745.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
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Patch

diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 25175a74b6b7..bca88715fada 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -32,9 +32,8 @@ 
 			next-level-cache = <&L2_CA7>;
 		};
 
-		L2_CA7: cache-controller@0 {
+		L2_CA7: cache-controller-0 {
 			compatible = "cache";
-			reg = <0>;
 			cache-unified;
 			cache-level = <2>;
 			power-domains = <&sysc R8A7745_PD_CA7_SCU>;