From patchwork Tue May 10 04:46:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: khiemnguyen X-Patchwork-Id: 9053971 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D5973BF29F for ; Tue, 10 May 2016 04:46:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3CEDF200E7 for ; Tue, 10 May 2016 04:46:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B89F2010B for ; Tue, 10 May 2016 04:46:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750982AbcEJEqL (ORCPT ); Tue, 10 May 2016 00:46:11 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:16406 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750858AbcEJEqK (ORCPT ); Tue, 10 May 2016 00:46:10 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie1.idc.renesas.com with ESMTP; 10 May 2016 13:46:07 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id C9BB442B96; Tue, 10 May 2016 13:46:07 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id B317B2806E; Tue, 10 May 2016 13:46:07 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id AB8D02806D; Tue, 10 May 2016 13:46:07 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac2.idc.renesas.com with ESMTP id PAA31412; Tue, 10 May 2016 13:46:07 +0900 X-IronPort-AV: E=Sophos;i="5.22,559,1449500400"; d="scan'208";a="210495767" Received: from unknown (HELO outside-ironport.rvc.renesas.com) ([172.29.139.110]) by relmlii1.idc.renesas.com with ESMTP; 10 May 2016 13:46:07 +0900 Received: from rvc-hts-01.rvc.renesas.com ([172.29.139.122]) by inside-ironport.rvc.renesas.com with ESMTP; 10 May 2016 11:46:06 +0700 Received: from [172.29.157.15] (172.29.157.15) by rvc-hts-01.rvc.renesas.com (172.29.139.120) with Microsoft SMTP Server id 8.3.83.0; Tue, 10 May 2016 11:46:06 +0700 Subject: [RFC 4/4] arm64: dts: r8a7795: Add Z clock scaling support To: Geert Uytterhoeven References: <1462372543-31835-1-git-send-email-geert+renesas@glider.be> <573166EB.70908@rvc.renesas.com> CC: Michael Turquette , Stephen Boyd , Simon Horman , Magnus Damm , Laurent Pinchart , "linux-clk@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , Toru Oishi , "Khiem Trong. Nguyen" From: Khiem Nguyen Message-ID: <5731678E.3080003@rvc.renesas.com> Date: Tue, 10 May 2016 11:46:06 +0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <573166EB.70908@rvc.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Z clock scaling support for CA57 in R8A7795 SoC. An OPP table is created with the supported frequency scaling. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Khiem Nguyen --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 7181db0..041d0f2 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -43,6 +43,8 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp_tb0>; }; a57_1: cpu@1 { @@ -52,6 +54,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp_tb0>; }; a57_2: cpu@2 { compatible = "arm,cortex-a57","arm,armv8"; @@ -60,6 +63,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp_tb0>; }; a57_3: cpu@3 { compatible = "arm,cortex-a57","arm,armv8"; @@ -68,6 +72,28 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp_tb0>; + }; + }; + + cluster0_opp_tb0: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; }; };