| Message ID | 61f6f4a4-e55c-06e0-cba1-7d90a556950a@cogentembedded.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote: > Define the Condor board dependent part of the I2C0 device node. > > The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders > and Analog Devices ADV7511W HDMI transmitter (but we're only describing > the former chips now). > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > =================================================================== > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > @@ -80,6 +80,28 @@ > clock-frequency = <32768>; > }; > > +&i2c0 { > + pinctrl-0 = <&i2c0_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > + clock-frequency = <400000>; > + > + io_expander0: gpio@20 { Hi Sergei, I'm a little confused about where 0x20 and 0x21 are derived from. Could you explain a little? > + compatible = "onnn,pca9654"; > + reg = <0x20>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + io_expander1: gpio@21 { > + compatible = "onnn,pca9654"; > + reg = <0x21>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > +}; > + > &mmc0 { > pinctrl-0 = <&mmc_pins>; > pinctrl-1 = <&mmc_pins_uhs>; > @@ -104,6 +126,11 @@ > function = "canfd0"; > }; > > + i2c0_pins: i2c0 { > + groups = "i2c0"; > + function = "i2c0"; > + }; > + > mmc_pins: mmc { > groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; > function = "mmc"; >
Hello! On 05/29/2018 04:10 PM, Simon Horman wrote: >> Define the Condor board dependent part of the I2C0 device node. >> >> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders >> and Analog Devices ADV7511W HDMI transmitter (but we're only describing >> the former chips now). >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> >> --- >> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts >> =================================================================== >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts >> @@ -80,6 +80,28 @@ >> clock-frequency = <32768>; >> }; >> >> +&i2c0 { >> + pinctrl-0 = <&i2c0_pins>; >> + pinctrl-names = "default"; >> + >> + status = "okay"; >> + clock-frequency = <400000>; >> + >> + io_expander0: gpio@20 { > > Hi Sergei, > > I'm a little confused about where 0x20 and 0x21 are derived from. > Could you explain a little? r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners. The schematics gives the 8-bit read/write addresses but we use uniform 7-bit I2C address in DTs. >> + compatible = "onnn,pca9654"; >> + reg = <0x20>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + io_expander1: gpio@21 { >> + compatible = "onnn,pca9654"; >> + reg = <0x21>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> +}; >> + >> &mmc0 { >> pinctrl-0 = <&mmc_pins>; >> pinctrl-1 = <&mmc_pins_uhs>;
On Tue, May 29, 2018 at 06:46:10PM +0300, Sergei Shtylyov wrote: > Hello! > > On 05/29/2018 04:10 PM, Simon Horman wrote: > > >> Define the Condor board dependent part of the I2C0 device node. > >> > >> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders > >> and Analog Devices ADV7511W HDMI transmitter (but we're only describing > >> the former chips now). > >> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > >> > >> --- > >> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++ > >> 1 file changed, 27 insertions(+) > >> > >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > >> =================================================================== > >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > >> @@ -80,6 +80,28 @@ > >> clock-frequency = <32768>; > >> }; > >> > >> +&i2c0 { > >> + pinctrl-0 = <&i2c0_pins>; > >> + pinctrl-names = "default"; > >> + > >> + status = "okay"; > >> + clock-frequency = <400000>; > >> + > >> + io_expander0: gpio@20 { > > > > Hi Sergei, > > > > I'm a little confused about where 0x20 and 0x21 are derived from. > > Could you explain a little? > > r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners. > The schematics gives the 8-bit read/write addresses but we use uniform 7-bit > I2C address in DTs. Thanks, this patch looks fine to me. However, I'd like to give others a chance to review it, and it is dependent on patch 1/2 where I have a different review question. Reviewed-by: Simon Horman <horms+renesas@verge.net.au> > >> + compatible = "onnn,pca9654"; > >> + reg = <0x20>; > >> + gpio-controller; > >> + #gpio-cells = <2>; > >> + }; > >> + > >> + io_expander1: gpio@21 { > >> + compatible = "onnn,pca9654"; > >> + reg = <0x21>; > >> + gpio-controller; > >> + #gpio-cells = <2>; > >> + }; > >> +}; > >> + > >> &mmc0 { > >> pinctrl-0 = <&mmc_pins>; > >> pinctrl-1 = <&mmc_pins_uhs>; >
Hi Sergei, On Mon, May 28, 2018 at 10:14 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Define the Condor board dependent part of the I2C0 device node. > > The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders > and Analog Devices ADV7511W HDMI transmitter (but we're only describing > the former chips now). > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Suggestion for future improvement below. > --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts > @@ -80,6 +80,28 @@ > clock-frequency = <32768>; > }; > > +&i2c0 { > + pinctrl-0 = <&i2c0_pins>; > + pinctrl-names = "default"; > + > + status = "okay"; > + clock-frequency = <400000>; > + > + io_expander0: gpio@20 { > + compatible = "onnn,pca9654"; > + reg = <0x20>; > + gpio-controller; > + #gpio-cells = <2>; The bindings don't mention this (the example does have it) the optional interrupts prototype. As this is wired to INTC-EX IRQ4, you may want to add that. Perhaps later, as r8a77980.dtsi doesn't have INTC-EX yet. > + }; > + > + io_expander1: gpio@21 { > + compatible = "onnn,pca9654"; > + reg = <0x21>; > + gpio-controller; > + #gpio-cells = <2>; Same for IRQ5. > + }; > +}; Gr{oetje,eeting}s, Geert
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -80,6 +80,28 @@ clock-frequency = <32768>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander0: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander1: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins_uhs>; @@ -104,6 +126,11 @@ function = "canfd0"; }; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc";
Define the Condor board dependent part of the I2C0 device node. The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders and Analog Devices ADV7511W HDMI transmitter (but we're only describing the former chips now). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+)