diff mbox

[12/31] ARM: dts: r8a7794: Remove unit-address and reg from integrated cache

Message ID 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d.1489999062.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d
Headers show

Commit Message

Simon Horman March 20, 2017, 8:57 a.m. UTC 
From: Geert Uytterhoeven <geert+renesas@glider.be>

The Cortex-A7 cache controller is an integrated controller, and thus the
device node representing it should not have a unit-addresses or reg
property.

Fixes: 34ea4b4a827b4ee7 ("ARM: dts: r8a7794: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7794.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
diff mbox

Patch

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 319c1069b7ee..cb31cd2232f9 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -56,9 +56,8 @@ 
 			next-level-cache = <&L2_CA7>;
 		};
 
-		L2_CA7: cache-controller@0 {
+		L2_CA7: cache-controller-0 {
 			compatible = "cache";
-			reg = <0>;
 			power-domains = <&sysc R8A7794_PD_CA7_SCU>;
 			cache-unified;
 			cache-level = <2>;