From patchwork Mon Jul 22 11:50:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13738713 X-Patchwork-Delegate: geert@linux-m68k.org Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [195.130.132.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85D0116D308 for ; Mon, 22 Jul 2024 11:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721649047; cv=none; b=cWHLE4Oz12pbfsd7RgNnR93SqMiFtIagS4ZshB11WO5MmQteDINQ8SfadkCYqgRLwpMx+M6fFsTNXyq82bWYquHWvqtPDZtDV8rINm8m1fzB0tTpX+HCAwOeP/8CmxW0X+t4cpnwMa2FZ/4TxK3Nn22L7t+pP+W1mcOuIeUJqXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721649047; c=relaxed/simple; bh=z17gZ01wDDMdBg4K87TjRj6f7/4kfXUvn2XGiqCD1QY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=c8TC4xMQBtA4aSvg/FXYTNOhI98QOoDT/cUH4zucbHFE3lwTc3AOrO8QCl5BjsgtuZCwZZ77fKWg1z6VW7jfMEmu8clRO40k+igqxgK0p9aoujmtSbwDHxHdmQ2aFLSznmHwPcLCjNYvK02FpGdUhylY+74OApioajf6ayKTu98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:173b:9414:53f5:de4c]) by xavier.telenet-ops.be with bizsmtp id qbqd2C0021wvoRx01bqd6R; Mon, 22 Jul 2024 13:50:37 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1sVrYY-002zB3-E8; Mon, 22 Jul 2024 13:50:37 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1sVrYq-0020iS-Tf; Mon, 22 Jul 2024 13:50:36 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Geert Uytterhoeven , Yoshihiro Shimoda Subject: [PATCH v2 13/15] clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type Date: Mon, 22 Jul 2024 13:50:33 +0200 Message-Id: <8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The variable PLL2 clock type was superseded by the more generic variable fractional 8.25 PLL clock type, and its sole user was converted. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda --- v2: - Add Reviewed-by. --- drivers/clk/renesas/rcar-gen4-cpg.c | 9 --------- drivers/clk/renesas/rcar-gen4-cpg.h | 1 - 2 files changed, 10 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index d3db602d7c5ec617..2a0f520d56b5aa96 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -440,15 +440,6 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, div = cpg_pll_config->pll1_div; break; - case CLK_TYPE_GEN4_PLL2_VAR: - /* - * PLL2 is implemented as a custom clock, to change the - * multiplier when cpufreq changes between normal and boost - * modes. - */ - return cpg_pll_clk_register(core->name, __clk_get_name(parent), - base, 2, &cpg_pll_v8_25_clk_ops); - case CLK_TYPE_GEN4_PLL2: mult = cpg_pll_config->pll2_mult; div = cpg_pll_config->pll2_div; diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h index 80a455e62cc1321e..2dadacacf3f911e2 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.h +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -13,7 +13,6 @@ enum rcar_gen4_clk_types { CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM, CLK_TYPE_GEN4_PLL1, CLK_TYPE_GEN4_PLL2, - CLK_TYPE_GEN4_PLL2_VAR, CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */ CLK_TYPE_GEN4_PLL3, CLK_TYPE_GEN4_PLL4,