From patchwork Mon Jul 18 10:53:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 9234403 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5173960756 for ; Mon, 18 Jul 2016 10:53:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 40A1D26B41 for ; Mon, 18 Jul 2016 10:53:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3552326C2F; Mon, 18 Jul 2016 10:53:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D69C26B41 for ; Mon, 18 Jul 2016 10:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751326AbcGRKxp (ORCPT ); Mon, 18 Jul 2016 06:53:45 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:36812 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750994AbcGRKxo (ORCPT ); Mon, 18 Jul 2016 06:53:44 -0400 Received: by mail-it0-f68.google.com with SMTP id j124so2459116ith.3; Mon, 18 Jul 2016 03:53:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=zE92ZwCYyF1JhiT4dbE2Rq9jgF8W9EvPwdM6NWbjCuo=; b=HtZlHspnSrOoznL95QKQwEeOWozJVyftoP+x5mEdTf28ulrlG3c7leX4UYHoW9nY1y hpWw8pTKnT1V4/yA0zCVjE9PJEkGNF1MjjKzzeboLLOl3SjI3/VDRiBFbOhQ0cqUr0vE Rk3qJd2Dk95qh/TU4vbKV2R2AaA6tzhSlKi9GRdxq6od/6Rout3scsPQz3L1K1EW93xL juG3JHzZ1pCH4ERhI1KY/3vtnno8tOJQPquBiF2XPX+0SENV9Qn/ndqzdrrVeHdhmTCG j7Bm02ixeAP61EGYem+TnkVcwE5j0BYmQ2/mv65XsWiK5x8fTCNAu8bOIHwu/NjsT+j0 JkcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=zE92ZwCYyF1JhiT4dbE2Rq9jgF8W9EvPwdM6NWbjCuo=; b=mLRCCC8dwWO/VRRy4mhs8E/YGZFzisPrstUQNKz6EoFM/2b/KLkGVYw3kKE0dYxLvv /5dhWhzAFqrS+AVBVN0qAvrYl1MvySRgNdB/1RWSCpvbylgEjrUjDThR9IeVWpWlfW+F qghKilnzpqiOFhyOiuOW/w8WJhGP1WPY3s0+orgy1iQ7X20UbfWfVAIPZO00d2ohGocX NXA1aoidpB3yKgGyN7nkva3WxdoGaT6vpQT/lmxkSp8r10DksL3k0Kxte3cQ2JBpYqVo wRwlnYvhy6lvM85ik9XyPcqGO6spXYM1gMiDwS/+S+3mktf00hXHhRGDsi0Uj1rUyNI5 bNcA== X-Gm-Message-State: ALyK8tIOCD9HMEC2tuD4DWcHmjEcvKuzykYPZHvWq3xg9daX8M03wgVI1Zs7l+eTYc4B0vBAxAVZ3N5LXpAjDw== X-Received: by 10.36.34.14 with SMTP id o14mr34544843ito.11.1468839222807; Mon, 18 Jul 2016 03:53:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.3.232 with HTTP; Mon, 18 Jul 2016 03:53:42 -0700 (PDT) In-Reply-To: <1468380049-5712-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1468380049-5712-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> From: Geert Uytterhoeven Date: Mon, 18 Jul 2016 12:53:42 +0200 X-Google-Sender-Auth: tO2C1f9p7NBDJFQyE_mgPpMxgXs Message-ID: Subject: Re: [PATCH] clk: renesas: r8a7795: Fix SD clocks To: Yoshihiro Shimoda , Wolfram Sang , Dirk Behme Cc: Michael Turquette , Stephen Boyd , linux-clk , Geert Uytterhoeven , Simon Horman , Linux-Renesas Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Shimoda-san, On Wed, Jul 13, 2016 at 5:20 AM, Yoshihiro Shimoda wrote: > According to the datasheet, SDn clocks are from the SDSRC clock. And > the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal > core clock. Otherwise, since the sdhi driver will calculate clock for > a sd card using the wrong parent clock rate, and then performance will > be not good. > > Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support") although this won't apply to v4.6 as-is, due to the move from drivers/clk/shmobile/ to drivers/clk/renesas, and s/DEF_SD/DEF_GEN3_SD/. This causes the following changes: - sdif0 1 2 12500000 0 0 zx 0 0 399999984 0 0 zt 0 0 199999992 0 0 ztrd2 0 0 66666664 0 0 ztr 0 0 133333328 0 0 + .sdsrc 2 2 399999984 0 0 + sd3 1 1 6250000 0 0 + sdif3 1 2 6250000 0 0 + sd2 0 0 49999998 0 0 + sdif2 0 0 49999998 0 0 + sd1 0 0 49999998 0 0 + sdif1 0 0 49999998 0 0 + sd0 1 1 6250000 0 0 + sdif0 1 2 6250000 0 0 .s3 3 3 133333328 0 0 s3d4 5 9 33333332 0 0 scu-all 0 12 33333332 0 0 Note that I still have a Salvator-X with a 16.67 MHz i.s.o. 33.33 Mhz crystal. Wolfram, Dirk: any comments? Thanks! > --- > drivers/clk/renesas/r8a7795-cpg-mssr.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c > index ca5519c..5f99f7c 100644 > --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c > @@ -91,6 +91,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { > DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), > DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), > DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), > + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), > > /* Core Clock Outputs */ > DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), > @@ -109,10 +110,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { > DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), > DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), > > - DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074), > - DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078), > - DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268), > - DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c), > + DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x0074), > + DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x0078), > + DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x0268), > + DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x026c), > > DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), > DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), Gr{oetje,eeting}s, Geert Acked-by: Dirk Behme Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang --- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds --- clk_summary.old 2016-07-18 12:45:07.788501000 +0200 +++ clk_summary 2016-07-18 12:47:43.279660000 +0200 @@ -34,23 +34,24 @@ .pll3 0 0 1599999936 0 0 .pll2 0 0 1199999952 0 0 .pll1 1 1 1599999936 0 0 - .pll1_div2 5 5 799999968 0 0 + .pll1_div2 4 4 799999968 0 0 hdmi 0 0 24999999 0 0 hdmi0 0 0 24999999 0 0 hdmi1 0 0 24999999 0 0 cl 0 0 16666666 0 0 - sd3 1 1 12500000 0 0 - sdif3 1 2 12500000 0 0 - sd2 0 0 99999996 0 0 - sdif2 0 0 99999996 0 0 - sd1 0 0 99999996 0 0 - sdif1 0 0 99999996 0 0 - sd0 1 1 12500000 0 0