| Message ID | a5bd4148f92806f7c8e577d383370f810315f586.1665155947.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | a4290d407aa9fd174d8053878783d466d3124e38 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock | expand |
On Fri, Oct 07, 2022 at 05:20:03PM +0200, Geert Uytterhoeven wrote: > As serial communication requires a clock signal, the High Speed Serial > Communication Interfaces with FIFO (HSCIF) are clocked by a clock that > is not affected by Spread Spectrum or Fractional Multiplication. > > Hence change the clock input for the HSCIF0 Baud Rate Generator internal > clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the > same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. > > Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Do we need to wait for the clarification about the docs mentioned in another thread?
Hi Wolfram, On Mon, Oct 10, 2022 at 9:56 AM Wolfram Sang <wsa@kernel.org> wrote: > On Fri, Oct 07, 2022 at 05:20:03PM +0200, Geert Uytterhoeven wrote: > > As serial communication requires a clock signal, the High Speed Serial > > Communication Interfaces with FIFO (HSCIF) are clocked by a clock that > > is not affected by Spread Spectrum or Fractional Multiplication. > > > > Hence change the clock input for the HSCIF0 Baud Rate Generator internal > > clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the > > same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. > > > > Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks! > Do we need to wait for the clarification about the docs mentioned in > another thread? This one matches the docs ;-) It's the module clock's parent in the clock driver which doesn't seem to match actual hardware. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index edabd1519ccc979d..c941054f4980667b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -360,7 +360,7 @@ hscif0: serial@e6540000 { reg = <0 0xe6540000 0 96>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x31>, <&dmac0 0x30>,
As serial communication requires a clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the clock input for the HSCIF0 Baud Rate Generator internal clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes: 987da486d84a5643 ("arm64: dts: renesas: Add Renesas R8A779G0 SoC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- For full proper operation, this depends on "[PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks"[1]. However, as the "brg_int" clock is optional, the serial driver will keep on functioning without it, and just resort to a less optimal clock input/divider combination, which is still good enough for the serial console. [1] https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)