diff mbox series

[2/5] arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores

Message ID c2a38a0da74915bf2a9171e53886c83a1c732934.1706796979.git.geert+renesas@glider.be (mailing list archive)
State Mainlined
Commit 7db43283be5364e07f8d2571a11789a2af086b12
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: r8a779h0: Add full CA76 CPU core support | expand

Commit Message

Geert Uytterhoeven Feb. 1, 2024, 2:19 p.m. UTC 
From: Duy Nguyen <duy.nguyen.rh@renesas.com>

Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Rename L3_CA76_0 label to L3_CA76,
  - Move psci node to preserve sort order (alphabetical),
  - Drop GIC_CPU_MASK_SIMPLE changes, as GICv3 PPI interrupt specifiers
    have no such masks.
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 50 +++++++++++++++++++++++
 1 file changed, 50 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index f47695158d991288..88c5dcbc38d59dab 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -18,12 +18,57 @@  cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a76_0>;
+				};
+				core1 {
+					cpu = <&a76_1>;
+				};
+				core2 {
+					cpu = <&a76_2>;
+				};
+				core3 {
+					cpu = <&a76_3>;
+				};
+			};
+		};
+
 		a76_0: cpu@0 {
 			compatible = "arm,cortex-a76";
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
+		};
+
+		a76_1: cpu@100 {
+			compatible = "arm,cortex-a76";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
+			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
+		};
+
+		a76_2: cpu@200 {
+			compatible = "arm,cortex-a76";
+			reg = <0x200>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
+			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
+		};
+
+		a76_3: cpu@300 {
+			compatible = "arm,cortex-a76";
+			reg = <0x300>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
+			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
 		};
 
 		L3_CA76: cache-controller {
@@ -53,6 +98,11 @@  pmu-a76 {
 		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
 	/* External SCIF clock - to be overridden by boards that provide it */
 	scif_clk: scif-clk {
 		compatible = "fixed-clock";