diff mbox series

arm64: dts: renesas: r8a779g0: Restore sort order

Message ID ccd215c1146b84c085908e01966f7036be51afa8.1737370801.git.geert+renesas@glider.be (mailing list archive)
State New
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: r8a779g0: Restore sort order | expand

Commit Message

Geert Uytterhoeven Jan. 20, 2025, 11:09 a.m. UTC 
Numerical by unit address, but grouped by type.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-devel for v6.15.

 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 80 +++++++++++------------
 1 file changed, 40 insertions(+), 40 deletions(-)

Comments

Niklas Söderlund Jan. 20, 2025, 12:55 p.m. UTC | #1 
Hi Geert,

Thanks for your work.

On 2025-01-20 12:09:12 +0100, Geert Uytterhoeven wrote:
> Numerical by unit address, but grouped by type.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
> To be queued in renesas-devel for v6.15.
> 
>  arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 80 +++++++++++------------
>  1 file changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> index 89049e40086c2d41..cbc4680e497734d3 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -2171,6 +2171,24 @@ fcpvd1: fcp@fea11000 {
>  			iommus = <&ipmmu_vi1 7>;
>  		};
>  
> +		fcpvx0: fcp@fedb0000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xfedb0000 0 0x200>;
> +			clocks = <&cpg CPG_MOD 1100>;
> +			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
> +			resets = <&cpg 1100>;
> +			iommus = <&ipmmu_vi1 24>;
> +		};
> +
> +		fcpvx1: fcp@fedb8000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xfedb8000 0 0x200>;
> +			clocks = <&cpg CPG_MOD 1101>;
> +			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
> +			resets = <&cpg 1101>;
> +			iommus = <&ipmmu_vi1 25>;
> +		};
> +
>  		vspd0: vsp@fea20000 {
>  			compatible = "renesas,vsp2";
>  			reg = <0 0xfea20000 0 0x7000>;
> @@ -2193,6 +2211,28 @@ vspd1: vsp@fea28000 {
>  			renesas,fcp = <&fcpvd1>;
>  		};
>  
> +		vspx0: vsp@fedd0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfedd0000 0 0x8000>;
> +			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 1028>;
> +			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
> +			resets = <&cpg 1028>;
> +
> +			renesas,fcp = <&fcpvx0>;
> +		};
> +
> +		vspx1: vsp@fedd8000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfedd8000 0 0x8000>;
> +			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 1029>;
> +			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
> +			resets = <&cpg 1029>;
> +
> +			renesas,fcp = <&fcpvx1>;
> +		};
> +
>  		du: display@feb00000 {
>  			compatible = "renesas,du-r8a779g0";
>  			reg = <0 0xfeb00000 0 0x40000>;
> @@ -2453,46 +2493,6 @@ port@1 {
>  			};
>  		};
>  
> -		fcpvx0: fcp@fedb0000 {
> -			compatible = "renesas,fcpv";
> -			reg = <0 0xfedb0000 0 0x200>;
> -			clocks = <&cpg CPG_MOD 1100>;
> -			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
> -			resets = <&cpg 1100>;
> -			iommus = <&ipmmu_vi1 24>;
> -		};
> -
> -		fcpvx1: fcp@fedb8000 {
> -			compatible = "renesas,fcpv";
> -			reg = <0 0xfedb8000 0 0x200>;
> -			clocks = <&cpg CPG_MOD 1101>;
> -			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
> -			resets = <&cpg 1101>;
> -			iommus = <&ipmmu_vi1 25>;
> -		};
> -
> -		vspx0: vsp@fedd0000 {
> -			compatible = "renesas,vsp2";
> -			reg = <0 0xfedd0000 0 0x8000>;
> -			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 1028>;
> -			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
> -			resets = <&cpg 1028>;
> -
> -			renesas,fcp = <&fcpvx0>;
> -		};
> -
> -		vspx1: vsp@fedd8000 {
> -			compatible = "renesas,vsp2";
> -			reg = <0 0xfedd8000 0 0x8000>;
> -			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&cpg CPG_MOD 1029>;
> -			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
> -			resets = <&cpg 1029>;
> -
> -			renesas,fcp = <&fcpvx1>;
> -		};
> -
>  		prr: chipid@fff00044 {
>  			compatible = "renesas,prr";
>  			reg = <0 0xfff00044 0 4>;
> -- 
> 2.43.0
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 89049e40086c2d41..cbc4680e497734d3 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -2171,6 +2171,24 @@  fcpvd1: fcp@fea11000 {
 			iommus = <&ipmmu_vi1 7>;
 		};
 
+		fcpvx0: fcp@fedb0000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb0000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1100>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+			resets = <&cpg 1100>;
+			iommus = <&ipmmu_vi1 24>;
+		};
+
+		fcpvx1: fcp@fedb8000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb8000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1101>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+			resets = <&cpg 1101>;
+			iommus = <&ipmmu_vi1 25>;
+		};
+
 		vspd0: vsp@fea20000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfea20000 0 0x7000>;
@@ -2193,6 +2211,28 @@  vspd1: vsp@fea28000 {
 			renesas,fcp = <&fcpvd1>;
 		};
 
+		vspx0: vsp@fedd0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd0000 0 0x8000>;
+			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1028>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+			resets = <&cpg 1028>;
+
+			renesas,fcp = <&fcpvx0>;
+		};
+
+		vspx1: vsp@fedd8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd8000 0 0x8000>;
+			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1029>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+			resets = <&cpg 1029>;
+
+			renesas,fcp = <&fcpvx1>;
+		};
+
 		du: display@feb00000 {
 			compatible = "renesas,du-r8a779g0";
 			reg = <0 0xfeb00000 0 0x40000>;
@@ -2453,46 +2493,6 @@  port@1 {
 			};
 		};
 
-		fcpvx0: fcp@fedb0000 {
-			compatible = "renesas,fcpv";
-			reg = <0 0xfedb0000 0 0x200>;
-			clocks = <&cpg CPG_MOD 1100>;
-			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
-			resets = <&cpg 1100>;
-			iommus = <&ipmmu_vi1 24>;
-		};
-
-		fcpvx1: fcp@fedb8000 {
-			compatible = "renesas,fcpv";
-			reg = <0 0xfedb8000 0 0x200>;
-			clocks = <&cpg CPG_MOD 1101>;
-			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
-			resets = <&cpg 1101>;
-			iommus = <&ipmmu_vi1 25>;
-		};
-
-		vspx0: vsp@fedd0000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfedd0000 0 0x8000>;
-			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 1028>;
-			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
-			resets = <&cpg 1028>;
-
-			renesas,fcp = <&fcpvx0>;
-		};
-
-		vspx1: vsp@fedd8000 {
-			compatible = "renesas,vsp2";
-			reg = <0 0xfedd8000 0 0x8000>;
-			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cpg CPG_MOD 1029>;
-			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
-			resets = <&cpg 1029>;
-
-			renesas,fcp = <&fcpvx1>;
-		};
-
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;