mbox series

[GIT,PULL] clk: renesas: Updates for v5.16 (take two)

Message ID cover.1634298371.git.geert+renesas@glider.be (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series [GIT,PULL] clk: renesas: Updates for v5.16 (take two) | expand

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v5.16-tag2

Message

Geert Uytterhoeven Oct. 15, 2021, 11:47 a.m. UTC
Hi Mike, Stephen,

The following changes since commit cc3e8f97bbd370b51b3bb7fec391d65d461d7d02:

  clk: renesas: r8a779a0: Add Z0 and Z1 clock support (2021-09-28 09:28:53 +0200)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v5.16-tag2

for you to fetch changes up to 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba:

  clk: renesas: r8a779[56]x: Add MLP clocks (2021-10-15 09:46:14 +0200)

----------------------------------------------------------------
clk: renesas: Updates for v5.16 (take two)

  - Add SPI Multi I/O Bus and SDHI clocks and resets on RZ/G2L,
  - Add SPI Multi I/O Bus (RPC) clocks on R-Car V3U,
  - Add MediaLB clocks on R-Car H3, M3-W/W+, and M3-N.

Thanks for pulling!
----------------------------------------------------------------
Andrey Gusakov (1):
      clk: renesas: r8a779[56]x: Add MLP clocks

Biju Das (2):
      clk: renesas: rzg2l: Add SDHI clk mux support
      clk: renesas: r9a07g044: Add SDHI clock and reset entries

Lad Prabhakar (1):
      clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller

Wolfram Sang (2):
      clk: renesas: cpg-lib: Move RPC clock registration to the library
      clk: renesas: r8a779a0: Add RPC support

 drivers/clk/renesas/r8a7795-cpg-mssr.c  |   1 +
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |   1 +
 drivers/clk/renesas/r8a77965-cpg-mssr.c |   1 +
 drivers/clk/renesas/r8a779a0-cpg-mssr.c |  32 +++++++++
 drivers/clk/renesas/r9a07g044-cpg.c     |  54 +++++++++++++++
 drivers/clk/renesas/rcar-cpg-lib.c      |  83 ++++++++++++++++++++++
 drivers/clk/renesas/rcar-cpg-lib.h      |   7 ++
 drivers/clk/renesas/rcar-gen3-cpg.c     |  89 +-----------------------
 drivers/clk/renesas/rzg2l-cpg.c         | 118 ++++++++++++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.h         |  19 +++++
 10 files changed, 318 insertions(+), 87 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Comments

Stephen Boyd Oct. 15, 2021, 10:01 p.m. UTC | #1
Quoting Geert Uytterhoeven (2021-10-15 04:47:36)
>         Hi Mike, Stephen,
> 
> The following changes since commit cc3e8f97bbd370b51b3bb7fec391d65d461d7d02:
> 
>   clk: renesas: r8a779a0: Add Z0 and Z1 clock support (2021-09-28 09:28:53 +0200)
> 
> are available in the Git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v5.16-tag2
> 
> for you to fetch changes up to 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba:
> 
>   clk: renesas: r8a779[56]x: Add MLP clocks (2021-10-15 09:46:14 +0200)
> 
> ----------------------------------------------------------------

Thanks. Pulled into clk-next