| Message ID | cover.1741362159.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [GIT,PULL] clk: renesas: Updates for v6.15 (take two) | expand |
Quoting Geert Uytterhoeven (2025-03-07 07:47:40) > Hi Mike, Stephen, > > The following changes since commit 9b12504e8c8c2f1f7e5f16afdd829603dd0c9508: > > clk: renesas: r9a09g047: Add CANFD clocks and resets (2025-02-20 17:42:03 +0100) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.15-tag2 > > for you to fetch changes up to e1a098330ef0555ad216e549a018d99aee7752c1: > > clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP (2025-03-06 16:39:31 +0100) > > ---------------------------------------------------------------- Thanks. Pulled into clk-next
Hi Mike, Stephen, The following changes since commit 9b12504e8c8c2f1f7e5f16afdd829603dd0c9508: clk: renesas: r9a09g047: Add CANFD clocks and resets (2025-02-20 17:42:03 +0100) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.15-tag2 for you to fetch changes up to e1a098330ef0555ad216e549a018d99aee7752c1: clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP (2025-03-06 16:39:31 +0100) ---------------------------------------------------------------- clk: renesas: Updates for v6.15 (take two) - Add DMA clocks and reset on RZ/V2H, - Add thermal (TSU) clock and reset on RZ/G3E, - Miscellaneous fixes and improvements. Thanks for pulling! ---------------------------------------------------------------- Biju Das (1): clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1 Fabrizio Castro (1): clk: renesas: r9a09g057: Add entries for the DMACs Geert Uytterhoeven (3): clk: renesas: cpg-mssr: Remove obsolete nullify check clk: renesas: rzg2l: Remove unneeded nullify checks clk: renesas: r7s9210: Distinguish clocks by clock type John Madieu (1): clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP drivers/clk/renesas/r7s9210-cpg-mssr.c | 10 ++++------ drivers/clk/renesas/r9a09g047-cpg.c | 3 +++ drivers/clk/renesas/r9a09g057-cpg.c | 24 ++++++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 5 ----- drivers/clk/renesas/rzg2l-cpg.c | 10 ---------- drivers/clk/renesas/rzv2h-cpg.c | 12 ++++++------ drivers/clk/renesas/rzv2h-cpg.h | 2 ++ 7 files changed, 39 insertions(+), 27 deletions(-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds