From patchwork Thu Dec 6 21:58:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10716857 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36C8918A7 for ; Thu, 6 Dec 2018 21:58:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 284582E95B for ; Thu, 6 Dec 2018 21:58:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1CB632E95E; Thu, 6 Dec 2018 21:58:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A90A22E95B for ; Thu, 6 Dec 2018 21:58:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726050AbeLFV6o (ORCPT ); Thu, 6 Dec 2018 16:58:44 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:55914 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725966AbeLFV6o (ORCPT ); Thu, 6 Dec 2018 16:58:44 -0500 Received: from penelope.horms.nl (unknown [64.124.208.80]) by kirsty.vergenet.net (Postfix) with ESMTPA id 1864D25BEE8; Fri, 7 Dec 2018 08:58:34 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1544133514; bh=Qlwuli52PuCg7VitnhOJ3dxbNI7G3C0ZZOiZgDfLFXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lw7hFwc+wOz7XB8DMvzJSaAh5OSdUIrW3sjLu8+/TmfFFkn3e4BSgkfPBd2RIz9XW e5KR8SMvagF07GpfQzlYB9RNg3KNELMHuCGtRz/FzBghARi2XNEsbx2+zdBId1aiaY hHpde6XjAl/HUwONtVsZjwTtV9pWdvZzNGJMGvn4= Received: by penelope.horms.nl (Postfix, from userid 7100) id 310CEE23291; Thu, 6 Dec 2018 13:58:31 -0800 (PST) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Biju Das , Simon Horman Subject: [PATCH 08/34] ARM: dts: r8a7744: Add SMP support Date: Thu, 6 Dec 2018 13:58:03 -0800 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Biju Das Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Also add cpu1 phandle node to the PMU interrupt-affinity property. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7744.dtsi | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 4d4ddbaba456..2cb6d8fa2fa0 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -49,6 +49,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -69,6 +70,25 @@ < 375000 1000000>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7744_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + L2_CA15: cache-controller-0 { compatible = "cache"; cache-unified; @@ -96,7 +116,7 @@ compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>; + interrupt-affinity = <&cpu0>, <&cpu1>; }; /* External SCIF clock */ @@ -250,6 +270,12 @@ #reset-cells = <1>; }; + apmu@e6152000 { + compatible = "renesas,r8a7744-apmu", "renesas,apmu"; + reg = <0 0xe6152000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + rst: reset-controller@e6160000 { compatible = "renesas,r8a7744-rst"; reg = <0 0xe6160000 0 0x100>; @@ -483,7 +509,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; @@ -520,10 +546,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */