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[6/8] ARM: dts: Renesas R9A06G032 SMP enable method

Message ID f8fc94dbcf2d166b865991afb6c827aa56dc0de2.1532345886.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit f8fc94dbcf2d166b865991afb6c827aa56dc0de2
Headers show
Series [GIT,PULL,v2] Renesas ARM Based SoC DT Updates for v4.19 | expand

Commit Message

Simon Horman July 23, 2018, 12:06 p.m. UTC 
From: Michel Pollet <michel.pollet@bp.renesas.com>

Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 339d0958011e..afe29c95a006 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -29,6 +29,8 @@ 
 			compatible = "arm,cortex-a7";
 			reg = <1>;
 			clocks = <&sysctrl 84>;
+			enable-method = "renesas,r9a06g032-smp";
+			cpu-release-addr = <0 0x4000c204>;
 		};
 	};