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bh=Pd8JWArOp7QBWH4Bz/BLcKRsri2NYRWh9cFvMPJbnHM=; b=ACdsO3CxbDWXqEvW5VgzkTy4w/CY0xTYdmFrw5RJWG0isVzRzXC+/AX90vYE67VnAc UP14qeiy++u24SQCcNE6jL4P67hdViJ6aD07es3Y9SLMw7Ed8Xifb7ryyc3K5Dnspi8g N24Nppl/I5VjFdizuk+5T1uwPQMfyBdKxwdf3S+NPaI2G+LFnHApw69m0ubj+lao8UMf V70SED/wHB1LHmGRk6f1tAr5lIUl8TBaVUQE1fnm0U2qzldJVXyBc6nIsSCu165k432r 8IaWJMZ6mKzwXP8UYvmm3U+2Rdx/BHCjmm4wRQY0+N1qjYtWkOBMUCBRHp9FvMl010pV Px0w== X-Gm-Message-State: APjAAAWuCwvIGKDJgXGwdgH3VdENyp9ySnrcvZ6ryT4HeUSwd555Rodp +XutnnL2DFzLN5iz2j7AulAsMmczMuA= X-Google-Smtp-Source: APXvYqzEyeNbWc8N7QcxEBLojkHQZOeGrYW8IOEn/1nRGuk/+U1H5bQn33IW4Xd/qK0vfFh8AJ5nHA== X-Received: by 2002:a65:484a:: with SMTP id i10mr35166470pgs.408.1556171716673; Wed, 24 Apr 2019 22:55:16 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id m16sm46332170pfi.29.2019.04.24.22.55.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Apr 2019 22:55:15 -0700 (PDT) From: Yash Shah To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, palmer@sifive.com Subject: [PATCH 0/2] L2 cache controller support for SiFive FU540 Date: Thu, 25 Apr 2019 11:24:54 +0530 Message-Id: <1556171696-7741-1-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190424_225518_162844_BE66AD3F X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, paul.walmsley@sifive.com MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch series adds an L2 cache controller driver with DT documentation for SiFive FU540-C000. These two patches were initially part of the patch series: 'L2 cache controller and EDAC support for SiFive SoCs' https://lkml.org/lkml/2019/4/15/320 In order to merge L2 cache controller driver without any dependency on EDAC, the L2 cache controller patches are re-posted seperately in this series. The patchset is based on Linux 5.1-rc2 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/L2_cache_controller branch of: https://github.com/yashshah7/riscv-linux.git Yash Shah (2): RISC-V: Add DT documentation for SiFive L2 Cache Controller RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 +++++ arch/riscv/mm/Makefile | 1 + arch/riscv/mm/sifive_l2_cache.c | 224 +++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt create mode 100644 arch/riscv/mm/sifive_l2_cache.c