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Wed, 18 Sep 2019 09:02:14 -0700 (PDT) From: Sagar Shrikant Kadam To: marek.vasut@gmail.com, tudor.ambarus@microchip.com, dwmw2@infradead.org, computersforpeace@gmail.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com Subject: [PATCH v9 0/2] mtd: spi-nor: add support for is25wp256 spi-nor flash Date: Wed, 18 Sep 2019 21:31:43 +0530 Message-Id: <1568822505-19297-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_090216_085486_5B8CB920 X-CRM114-Status: GOOD ( 12.73 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aou@eecs.berkeley.edu, palmer@sifive.com, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Sagar Shrikant Kadam , paul.walmsley@sifive.com, linux-riscv@lists.infradead.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org The patch series adds basic support for 32MiB spi-nor is25wp256 present on HiFive Unleashed A00 board. The flash device gets BFPT_DWORD1_ADDRESS_BYTES_3_ONLY from BFPT table for address width, whereas the flash can support 4 byte address width, so the address width is configured by using the post bfpt fixup hook as done for is25lp256 device in commit cf580a924005 ("mtd: spi-nor: fix nor->addr_width when its value configured from SFDP does not match the actual width") Patches are based on original work done by Wesley Terpstra and/or Palmer Dabbelt: https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b Erase/Read/Write operations are verified on HiFive Unleashed board using mtd and flash utils (v1.5.2): 1. mtd_debug : Options available are : erase/read/write. 2. flashcp : Single utility that erases flash, writes a file to flash and verifies the data back. The changes are available under branch dev/sagark/spi-nor-v9 at https://github.com/sagsifive/riscv-linux-hifive Revision history: V8<->V9: -Rebased this series to mainline v5.3-rc8 -Corrected number of sectors in the spi nor id table for is25wp256 device as suggested in the review. -The lock/unlock scheme in the V8 version of this series needs to have a more generic approach. These protection scheme patches are not included in this series, will submit those separately. V7<->V8: -Rebased this series on mainline v5.3-rc4. -Removed remaining func_reg reference from issi_lock as updating OTP region was dropped as part of V6. -Updated Reviewed-By tags to 1st and 2nd patch. V6<->V7: -Incorporated review comments from Vignesh. -Used post bfpt fixup hook as suggested by Vignesh. -Introduce SPI_NOR_HAS_BP3 to identify whether the flash has 4th bit protect bit. -Prefix generic flash access functions with spi_nor_xxxx. V5<->V6: -Incorporated review comments from Vignesh. -Set addr width based on device size and if SPI_NOR_4B_OPCODES is set. -Added 4th block protect identifier (SPI_NOR_HAS_BP3) to flash_info structure -Changed flash_info: flag from u16 to u32 to accommodate SPI_NOR_HAS_BP3 -Prefix newly added function with spi_nor_xxx. -Dropped write_fr function, as updating OTP bit's present in function register doesn't seem to be a good idea. -Set lock/unlock schemes based on whether the ISSI device has locking support and BP3 bit present. V4<->V5: -Rebased to linux version v5.2-rc1. -Updated heading of this cover letter with sub-system, instead of just plain "add support for is25wp256..." V3<->V4: -Extracted comman code and renamed few stm functions so that it can be reused for issi lock implementation. -Added function's to read and write FR register, for selecting Top/Bottom area. V2<->V3: -Rebased patch to mainline v5.1 from earlier v5.1-rc5. -Updated commit messages, and cover letter with reference to git URL and author information. -Deferred flash_lock mechanism and can go as separate patch. V1<-> V2: -Incorporated changes suggested by reviewers regarding patch/cover letter versioning, references of patch. -Updated cover letter with description for flash operations verified with these changes. -Add support for unlocking is25xxxxxx device. -Add support for locking is25xxxxxx device. v1: -Add support for is25wp256 device. Sagar Shrikant Kadam (2): mtd: spi-nor: add support for is25wp256 mtd: spi-nor: fix nor->addr_width for is25wp256 drivers/mtd/spi-nor/spi-nor.c | 9 ++++++++- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-)