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X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.236.52 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aou@eecs.berkeley.edu, sachin.ghadi@sifive.com, anup@brainfault.org, linux-kernel@vger.kernel.org, alexios.zavras@intel.com, Yash Shah , gregkh@linuxfoundation.org, tglx@linutronix.de, bp@suse.de, linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org The patchset includes 2 patches. Patch 1 implements cache_get_priv_group which make use of a generic ops structure to return a private attribute group for custom cacheinfo. Patch 2 implements a private attribute named "number_of_ways_enabled" in the cacheinfo framework. Reading this attribute returns the number of L2 cache ways enabled at runtime, This patchset is based on Linux v5.6-rc2 and tested on HiFive Unleashed board. v5: - Since WayEnable is 8bits, mask out and return only the last 8 bit in l2_largest_wayenabled() - Rebased on Linux v5.6-rc2 v4: - Rename "sifive_l2_largest_wayenabled" to "l2_largest_wayenabled" and make it a static function v3: - As per Anup Patel's suggestion[0], implement a new approach which uses generic ops structure. Hence addition of patch 1 to this series and corresponding changes to patch 2. - Dropped "riscv: dts: Add DT support for SiFive L2 cache controller" patch since it is already merged - Rebased on Linux v5.5-rc6 Changes in v2: - Rebase the series on v5.5-rc3 - Remove the reserved-memory node from DT [0]: https://lore.kernel.org/linux-riscv/CAAhSdy0CXde5s_ya=4YvmA4UQ5f5gLU-Z_FaOr8LPni+s_615Q@mail.gmail.com/ Yash Shah (2): riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure riscv: Add support to determine no. of L2 cache way enabled arch/riscv/include/asm/cacheinfo.h | 15 ++++++++++++++ arch/riscv/kernel/cacheinfo.c | 17 ++++++++++++++++ drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) create mode 100644 arch/riscv/include/asm/cacheinfo.h