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DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6141; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wzu4QgTPn6lqqRR6GN/hup32NRaDNGEWDiU0JSgutxdd9poU0OhKjci7L75RXDV2CVQ4rqLAtv3sDx0A0WCvLy1OY4j8J2ZB4KQAqbggp0eP1QD/+8ktxdPLgd4NHPt3j4NmjTEljcKrZ5LMP9Mg/5uIYhrZo7DTc3AFfFaA05TJqGaP94KihcIni3ju8U4IxPbNK77RLokWW1rOCAuKnoDMNyBxkv4QhMzTj03mAuHRjw00G50IzTOXY6XoO7d0BuRmy6bmnfSroi6+yAY/II+Yma6lY1k+modM5rQVtcfPi3w8RfWHLnHTl9GQcyVyH8rKfUDX9a2vbFFbgqfISQdR4bmHUBA+6cXDcjP4G2vIw4S7aSKPsrZNQ/D0jBeHvAhzagwkh5CCwz/fZQy3rTRt2UbXvFg+IWlHvzMiqdE= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 28dca770-55dc-499a-5891-08d6b10378ab X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Mar 2019 09:22:59.3101 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6141 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190325_022305_169309_59D56010 X-CRM114-Status: GOOD ( 14.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , "linux-kernel@vger.kernel.org" , Mike Rapoport , Christoph Hellwig , Atish Patra , Paul Walmsley , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patchset primarily extends initial page table setup using fixmap to boot Linux RISC-V kernel (64bit and 32bit) from any 4KB aligned address. We also add 32bit defconfig to allow people to try 32bit Linux RISC-V kernel as well. The patchset is based on Linux-5.1-rc2 and tested on SiFive Unleashed board and QEMU virt machine. It can also be found in riscv_setup_vm_v3 branch of https//github.com/avpatel/linux.git Changes since v2: - Dropped PATCH2 because we have separate fix for Linux-5.1-rcX - Moved PATCH5 to PATCH2 - Moved PATCH4 to PATCH3 - The "Booting kernel from any 4KB aligned address" is now PATCH4 Changes since v1: - Add kconfig option BOOT_PAGE_ALIGNED to enable 4KB aligned booting - Improved initial page table setup code to select best/biggest possible mapping size based on load address alignment - Added PATCH4 to remove redundant trampoline page table - Added PATCH5 to fix memory reservation in setup_bootmem() Anup Patel (4): RISC-V: Add separate defconfig for 32bit systems RISC-V: Fix memory reservation in setup_bootmem() RISC-V: Remove redundant trampoline page table RISC-V: Allow booting kernel from any 4KB aligned address arch/riscv/Kconfig | 12 + arch/riscv/configs/rv32_defconfig | 84 +++++++ arch/riscv/include/asm/fixmap.h | 5 + arch/riscv/include/asm/pgtable-64.h | 5 + arch/riscv/include/asm/pgtable.h | 5 + arch/riscv/kernel/head.S | 14 +- arch/riscv/kernel/setup.c | 4 +- arch/riscv/mm/init.c | 376 +++++++++++++++++++++++----- 8 files changed, 430 insertions(+), 75 deletions(-) create mode 100644 arch/riscv/configs/rv32_defconfig