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28 Oct 2020 16:13:15 -0700 IronPort-SDR: buavO+3n128wXApNGIFfrqEjjKBm1I1PnymmXX6X25/PUwDn5yG4TfLzSC3aE2blO728jSGeng ZYeuijWei4Rk96OnUtunZLZLpZ8I8ZF8kBAwFll7TWFGOFYd+USFDHf28rNgHOg1kK6CBbOvEg 2ne1I12LnBypDbBQB2RIMi+VZJRwgjVqnm/MHzx9HfJMpfW9eN7HbjCtMB8+TA8F7C6Ab31MPf ygcujc57MY7V/gNCT4VLsSKPv0htxzY3Vi3usUONWUKMZJTk01Q2pOZ1r1bYLYPudWSqa4oxUc U2k= WDCIronportException: Internal Received: from myd002180.ad.shared (HELO jedi-01.hgst.com) ([10.86.60.107]) by uls-op-cesaip01.wdc.com with ESMTP; 28 Oct 2020 16:28:07 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Date: Wed, 28 Oct 2020 16:27:56 -0700 Message-Id: <20201028232759.1928479-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201028_192808_562477_8B271A38 X-CRM114-Status: GOOD ( 16.98 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [216.71.154.45 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Albert Ou , Cyril.Jean@microchip.com, Daire McNamara , Anup Patel , Atish Patra , Rob Herring , Alistair Francis , Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, padmarao.begari@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This series adds minimal support for Microchip Polar Fire Soc Icicle kit. It is rebased on v5.10-rc1 and depends on clock support. Only MMC and ethernet drivers are enabled via this series. The idea here is to add the foundational patches so that other drivers can be added to on top of this. This series has been tested on Qemu and Polar Fire Soc Icicle kit. The following qemu series is necessary to test it on Qemu. The series can also be found at the following github repo. I noticed the latest version of mmc driver[2] hangs on the board with the latest clock driver. That's why, I have tested with the old clock driver available in the above github repo. [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html [2] https://www.spinics.net/lists/devicetree/msg383626.html Atish Patra (3): RISC-V: Add Microchip PolarFire SoC kconfig option RISC-V: Initial DTS for Microchip ICICLE board RISC-V: Enable Microchip PolarFire ICICLE SoC arch/riscv/Kconfig.socs | 7 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../microchip/microchip-icicle-kit-a000.dts | 313 ++++++++++++++++++ arch/riscv/configs/defconfig | 4 + 5 files changed, 327 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/Makefile create mode 100644 arch/riscv/boot/dts/microchip/microchip-icicle-kit-a000.dts --- 2.25.1