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19 Mar 2021 15:42:01 -0700 IronPort-SDR: WtbzaVxxfmKWmKaOXP5pznJullm99yE0eUrF+pcc3X67ZA2teNqDg/5mqnH/pqLQ8p5bDiZJ7Y BKlWPB4SQvzjLVYenj3iT1eQSp0NJicFWRa7O3+kedm05yHtuGFl1jtrHJIoX2XyOHR/zDP3/l YLl7zXgwedkr5FFawG/emmG5xrR92bfhr6KKCOgLIEcUMuEEX5hLKCyazVIlqoAunaiPwYvmro 2ugrHrYOV3phGH2iUpRBfBcdB+ENC8X2zA0PC64n+TgiG7O1/VQfn9kgQYeDpSl/6j93PX4itp gm0= WDCIronportException: Internal Received: from ind002560.ad.shared (HELO jedi-01.hgst.com) ([10.86.48.105]) by uls-op-cesaip02.wdc.com with ESMTP; 19 Mar 2021 16:01:30 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Alexander Shishkin , Anup Patel , Ard Biesheuvel , Arnaldo Carvalho de Melo , Guo Ren , Kefeng Wang , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [RFC 0/6] Improve RISC-V Perf support using SBI PMU extension Date: Fri, 19 Mar 2021 16:01:00 -0700 Message-Id: <20210319230106.2186694-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210319_230131_912427_58DCA27E X-CRM114-Status: GOOD ( 20.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series adds improved perf support for RISC-V based system using SBI PMU extension[1]. It is based on a platform driver instead of a existing arch specific implementation. The core platform driver is implemented in such a way that most of the generic event handling is done in the core driver while individual PMUs need to only implement necessary features specific to the PMU. This is easily extensible and any future RISC-V PMU implementation can leverage this. Currently, SBI PMU driver & legacy PMU driver are implemented as a part of this series. The SBI based driver provides more advanced features such as event configure start/stop. This version does not implement counter overflow & filtering yet. That will implemented in the future on top of this series using "Sscof" extension. The RISC-V perf documentation will also be updated at that time with all the bits. The legacy driver tries to reimplement the existing minimal perf under a new config to maintain backward compatibility. This implementation only allows monitoring of always running cycle/instruction counters. Moreover, they can not be started or stopped. In general, this is very limited and not very useful. That's why, I am not very keen to carry the support into the new driver. However, I don't want to break perf for any existing hardware platforms. If nobody really uses perf currently, I will be happy to drop PATCH 4. This series has been tested in Qemu on RV64 only. Qemu[2] & OpenSBI [3] patches are required to test it. Qemu changes are not backward compatible. That means, you can not use perf anymore on older Qemu versions with latest OpenSBI and/or Kernel. However, newer kernel will just use legacy pmu driver if old OpenSBI is detected or hardware doesn't implement mcountinhibit. Here is an output of perf stat while running hackbench. [root@fedora-riscv riscv]# perf stat -e r8000000000000007 -e r8000000000000006 \ -e r0000000000000002 -e r0000000000000004 -e branch-misses -e cache-misses \ -e cycles -e instructions ./hackbench -pipe 15 process 15 Running with 15*40 (== 600) tasks. Time: 1.548 Performance counter stats for './hackbench -pipe 15 process 15': 7,103 r8000000000000007 (62.56%) --> SBI_PMU_FW_IPI_RECVD 7,767 r8000000000000006 (12.19%) --> SBI_PMU_FW_IPI_SENT 0 r0000000000000002 (24.79%) --> a custom raw event described in DT r0000000000000004 (0.00%) --> non-supported raw event described in DT 0 branch-misses (12.65%) 0 cache-misses (25.36%) 27,978,868,702 cycles (38.12%) 27,849,527,556 instructions # 1.00 insn per cycle (50.46%) 2.431195184 seconds time elapsed 1.553153000 seconds user 13.615924000 seconds sys The patches can also be found in the github[4]. [1] https://lists.riscv.org/g/tech-unixplatformspec/message/598 [2] https://github.com/atishp04/qemu/tree/riscv_pmu_v1 [3] https://github.com/atishp04/opensbi/tree/riscv_pmu_v1 [4] https://github.com/atishp04/linux/tree/riscv_pmu_v1 Atish Patra (6): RISC-V: Remove the current perf implementation RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Add a perf core platform driver RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add perf platform driver based on SBI PMU extension arch/riscv/Kconfig | 13 - arch/riscv/include/asm/csr.h | 58 ++++ arch/riscv/include/asm/perf_event.h | 72 ----- arch/riscv/include/asm/sbi.h | 80 +++++ arch/riscv/kernel/Makefile | 1 - arch/riscv/kernel/perf_event.c | 485 ---------------------------- drivers/perf/Kconfig | 25 ++ drivers/perf/Makefile | 5 + drivers/perf/riscv_pmu.c | 397 +++++++++++++++++++++++ drivers/perf/riscv_pmu_legacy.c | 88 +++++ drivers/perf/riscv_pmu_sbi.c | 464 ++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + include/linux/perf/riscv_pmu.h | 61 ++++ 13 files changed, 1179 insertions(+), 571 deletions(-) delete mode 100644 arch/riscv/kernel/perf_event.c create mode 100644 drivers/perf/riscv_pmu.c create mode 100644 drivers/perf/riscv_pmu_legacy.c create mode 100644 drivers/perf/riscv_pmu_sbi.c create mode 100644 include/linux/perf/riscv_pmu.h --- 2.25.1