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[99.13.229.45]) by smtp.gmail.com with ESMTPSA id p14sm422100oov.0.2021.11.18.00.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Nov 2021 00:40:03 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Heinrich Schuchardt , Kefeng Wang , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley Subject: [PATCH v5 0/5] Add SBI v0.2 support for KVM Date: Thu, 18 Nov 2021 00:39:07 -0800 Message-Id: <20211118083912.981995-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211118_004006_866986_2A56C82F X-CRM114-Status: GOOD ( 13.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Supervisor Binary Interface(SBI) specification[1] now defines a base extension that provides extendability to add future extensions while maintaining backward compatibility with previous versions. The new version is defined as 0.2 and older version is marked as 0.1. This series adds following features to RISC-V Linux KVM. 1. Adds support for SBI v0.2 in KVM 2. SBI Hart state management extension (HSM) in KVM 3. Ordered booting of guest vcpus in guest Linux This series is based on base KVM series which is already part of the kvm-next[2]. Guest kernel needs to also support SBI v0.2 and HSM extension in Kernel to boot multiple vcpus. Linux kernel supports both starting v5.7. In absense of that, guest can only boot 1 vcpu. Changes from v4->v5: 1. Added reviewed-by tags. 2. Removed the redundant kvm_cpu_context pointer sanity check. Changes from v3->v4: 1. Fixed the commit text title. 2. Removed a redundant memory barrier from patch 4. 3. Replaced preempt_enable/disable with get_cpu/put_cpu. 4. Renamed the exixting implementation as v01 instead of legacy. Changes from v2->v3: 1. Rebased on the latest merged kvm series. 2. Dropped the reset extension patch because reset extension is not merged in kernel. However, my tree[3] still contains it in case anybody wants to test it. Changes from v1->v2: 1. Sent the patch 1 separately as it can merged independently. 2. Added Reset extension functionality. Tested on Qemu and Rocket core FPGA. [1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc [3] https://github.com/atishp04/linux/tree/kvm_sbi_v05_reset [4] https://github.com/atishp04/linux/tree/kvm_sbi_v05 Atish Patra (5): RISC-V: KVM: Mark the existing SBI implementation as v01 RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file RISC-V: KVM: Add SBI v0.2 base extension RISC-V: KVM: Add v0.1 replacement SBI extensions defined in v02 RISC-V: KVM: Add SBI HSM extension in KVM arch/riscv/include/asm/kvm_vcpu_sbi.h | 33 ++++ arch/riscv/include/asm/sbi.h | 9 ++ arch/riscv/kvm/Makefile | 4 + arch/riscv/kvm/vcpu.c | 23 +++ arch/riscv/kvm/vcpu_sbi.c | 211 ++++++++++++-------------- arch/riscv/kvm/vcpu_sbi_base.c | 70 +++++++++ arch/riscv/kvm/vcpu_sbi_hsm.c | 105 +++++++++++++ arch/riscv/kvm/vcpu_sbi_replace.c | 133 ++++++++++++++++ arch/riscv/kvm/vcpu_sbi_v01.c | 126 +++++++++++++++ 9 files changed, 599 insertions(+), 115 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_sbi.h create mode 100644 arch/riscv/kvm/vcpu_sbi_base.c create mode 100644 arch/riscv/kvm/vcpu_sbi_hsm.c create mode 100644 arch/riscv/kvm/vcpu_sbi_replace.c create mode 100644 arch/riscv/kvm/vcpu_sbi_v01.c --- 2.33.1