From patchwork Mon Jan 17 11:07:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12715176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CAC5C433EF for ; Mon, 17 Jan 2022 11:06:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=j6YzCz20vQyiBlJC8uVShQAQ4pcq/ImGkACAgAbE/1k=; b=iYlIALErH9tfgd G710LJTHpIkJUrgNC9BKDZ1UvYsRi4R2K3RdlgdNXdtZdh9Qc86bmEwtpnKec3G1isXKahCnZowiz CDFyIOeaNHZqY6YwuwHqBa8MIWrgtYVuHmwr2YVY3b0dlXCr8sfXr59rzZ69qi45T3zjrSNgYiUMh 2xLBV0jJ3uyE/FsxATMYONffG8AfGYeqvZS/b5oaF0I7+P2X3dgml0eP+Bri570d28vlriOG4lc6q y8muPjTTN2ApsQE573ZGQw58RfrH8vFyQf6T+5s8UGOlMcSCBM9J8A5Tlev7EvrN0bCsw4VdGafa/ 4k6QF+DscFCrbOrEzLEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9Ppp-00Eaf4-FX; Mon, 17 Jan 2022 11:06:01 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9Ppk-00Eae4-E8 for linux-riscv@lists.infradead.org; Mon, 17 Jan 2022 11:05:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642417556; x=1673953556; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=gWCB2jSI8ZbCAofIfIvhZNSEbC/cw4Yx/YGwRjsWNEQ=; b=yHV1LlUGu/PA1639wC6yMhFuDe8r+iQy7qJqrEy/BSZ6jnbhQ1dvPodH Tyes9tUFrlxdfYbjVoa725NsjXh+XUf2YiQqeJIPCyJvp1dQHmo8C4BCo RaTKe6Wc+gKzljQd8t6ZGht9GTSddfWmxBgb0fGSojmrY50iqefTvjB38 Qjh3PGfT+vIe3bYNk4Ku+cyiLtlXaLyZEzkCJyA8fsjWrQOuzqjBXT9Tt XhQqQgD/bkDQ+Gjf1/PbgVcKVqbVo6EHbP8hHlVqeiMYuzUt4adLQhnxw 1Ck9K8lSTWBEmBrXyte+HyNHN09BqZLOcjdKJ7dV3p8Wfqi0eXxHkFcqA w==; IronPort-SDR: AfRy/Y5tMEri9D+SlVeOwzlpEo33GD+ODIq9O2nmTIUR3aeUAgeqyoBpBhGw444MilL5dYe7ji LbvwvGAOlLG4gMz6bs4gUuCi1XlX+jkZ/RAhcTeHkD9og86LIFz/JQB9Dkhl+H+B9c8xQBRJ3v fuiFdj4x1zC80djpIGaEujzpTWMGFLi7EAScLOhYF0qlz+GN5XV1rP1wapcWSEHAJPAjAqKTZ2 Eww8JPdnydDOisFWeylOtDFOD7ftsJ1ll89be4nI8au6OF/s/8Zb/acd2CxkwOmQc/pR2uY2VQ anLH9qaEbvQjVQmuqX4gfdi+ X-IronPort-AV: E=Sophos;i="5.88,295,1635231600"; d="scan'208";a="150422938" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Jan 2022 04:05:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 17 Jan 2022 04:05:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 17 Jan 2022 04:05:41 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 00/14] Update the Icicle Kit device tree Date: Mon, 17 Jan 2022 11:07:41 +0000 Message-ID: <20220117110755.3433142-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220117_030556_542092_D51A692A X-CRM114-Status: GOOD ( 13.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric. Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string appears un-documented" errors. Depends on mpfs clock driver series [1] to provide: dt-bindings/clock/microchip,mpfs-clock.h and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next. Additionally, the interrupt-extended warnings on the plic/clint are cleared by [2] & [3]. [1] https://lore.kernel.org/linux-clk/20211216140022.16146-1-conor.dooley@microchip.com/T/ [2] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/ [3] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/ Changes from v3: - drop "mailbox: change mailbox-mpfs compatible string", already upstream: commit f10b1fc0161cd99e - fix copy paste error in microchip,mpfs-mailbox dt-binding - remove whitespace in syscontroller dt entry Changes from v2: - dropped plic int header & corresponding defines in dts{,i} - use $ref to drmode in mpfs-musb binding - split changes to dts{,i} again: functional changes to existing elements now are in a new patch - drop num-cs property in mpfs-spi binding - dont make the system controller a simple-mfd - move the separate bindings for rng/generic system services into the system controller binding - added an instance corei2c as i2c2 in the fabric dtsi - add version numbering to corepwm and corei2c compat string (-rtl-vN) Conor Dooley (14): dt-bindings: soc/microchip: update syscontroller compatibles dt-bindings: soc/microchip: add services as children of sys ctrlr dt-bindings: i2c: add bindings for microchip mpfs i2c dt-bindings: rtc: add bindings for microchip mpfs rtc dt-bindings: gpio: add bindings for microchip mpfs gpio dt-bindings: spi: add bindings for microchip mpfs spi dt-bindings: usb: add bindings for microchip mpfs musb dt-bindings: pwm: add microchip corepwm binding riscv: dts: microchip: use clk defines for icicle kit riscv: dts: microchip: add fpga fabric section to icicle kit riscv: dts: microchip: refactor icicle kit device tree riscv: dts: microchip: update peripherals in icicle kit device tree riscv: dts: microchip: add new peripherals to icicle kit device tree MAINTAINERS: update riscv/microchip entry .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 ++++++ .../bindings/i2c/microchip,mpfs-i2c.yaml | 55 ++++ ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +- .../bindings/pwm/microchip,corepwm.yaml | 75 +++++ .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++ .../microchip,mpfs-sys-controller.yaml | 73 +++++ ...icrochip,polarfire-soc-sys-controller.yaml | 35 --- .../bindings/spi/microchip,mpfs-spi.yaml | 52 ++++ .../bindings/usb/microchip,mpfs-musb.yaml | 59 ++++ MAINTAINERS | 2 + .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++ .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++-- .../boot/dts/microchip/microchip-mpfs.dtsi | 262 +++++++++++++++--- arch/riscv/configs/icicle_kit_defconfig | 134 +++++++++ 14 files changed, 932 insertions(+), 104 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi create mode 100644 arch/riscv/configs/icicle_kit_defconfig