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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id bx10-20020a0568081b0a00b002d70da1ac54sm5936852oib.19.2022.02.28.01.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Feb 2022 01:42:41 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , kvm-riscv@lists.infradead.org, Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [RFC PATCH 0/6] Add Sstc extension support Date: Mon, 28 Feb 2022 01:42:27 -0800 Message-Id: <20220228094234.3773153-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220228_014243_131613_6767EB4F X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series implements Sstc extension support which was ratified recently. Before the Sstc extension, an SBI call is necessary to generate timer interrupts as only M-mode have access to the timecompare registers. Thus, there is significant latency to generate timer interrupts at kernel. For virtualized enviornments, its even worse as the KVM handles the SBI call and uses a software timer to emulate the timecomapre register. Sstc extension solves both these problems by defining a stimecmp/vstimecmp at supervisor (host/guest) level. It allows kernel to program a timer and recieve interrupt without supervisor execution enviornment (M-mode/HS mode) intervention. To maintain backward compatibility, KVM directly updates the vstimecmp if older kernel without sstc support is running in guest. Similary, the M-mode firmware(OpenSBI) uses stimecmp for older kernel without sstc support. The PATCH 1 & 2 enables the basic infrastructure around Sstc extension while PATCH 3 lets kernel use the Sstc extension if it is available in hardware. PATCH 4 & 5 adds the infrastructure for KVM to use sstc while PATCH 6 actually uses the Sstc extension if available. This series has been tested on Qemu(RV32 & RV64) with additional patches in OpenSBI[2] and Qemu[3]. This series can also be found at [4]. [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view [2] https://github.com/atishp04/opensbi/tree/sstc_v1 [3] https://github.com/atishp04/qemu/tree/sstc_v1 [3] https://github.com/atishp04/linux/tree/sstc_v1 Atish Patra (6): RISC-V: Add SSTC extension CSR details RISC-V: Enable sstc extension parsing from DT RISC-V: Prefer sstc extension if available RISC-V: Restrict the isa field in config register to base extensions RISC-V: KVM: Introduce ISA extension register RISC-V: KVM: Support sstc extension arch/riscv/include/asm/csr.h | 11 ++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_timer.h | 3 +- arch/riscv/include/asm/timex.h | 2 + arch/riscv/include/uapi/asm/kvm.h | 22 ++++ arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 4 +- arch/riscv/kvm/main.c | 8 ++ arch/riscv/kvm/vcpu.c | 111 ++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_replace.c | 10 +- arch/riscv/kvm/vcpu_timer.c | 136 +++++++++++++++++++++++- drivers/clocksource/timer-riscv.c | 22 +++- 13 files changed, 323 insertions(+), 12 deletions(-) --- 2.30.2