From patchwork Fri Apr 29 10:40:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12831791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B1CFC433FE for ; Fri, 29 Apr 2022 10:41:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=pbtNcOM4biprv5msoXo8uw9MvhX8gRr/vBmv/tTWC3k=; b=IGIZFq3Zbh/Eb3 XG5FpTKH+raM7igLmfBFN1fRNqrHSDQ9SXKTELF9LmFJrAvHhj13aF+uwFynUL8WalhQH2IPlsOXf cqzuN4iwyzGL+mOo/BCyNTkZ5hqDT0QMOw8Ee6I6p9ZVQsd+JpxTLu7GctIsQXdUcLOvxCFD4zA74 ilMev+pJTau7W03hdpAEJa01u7QVSg6zO7N3mWxgCaOPGPFSlyou4e01Ao8U9rSM38KVnnHBomJnc PmHJBWqXDdbVJ2pjGneoDvn9sTPMhBEOAd0VIRxxwSRRok1Hgn8Z8Cp3fEYjY/5Ooc1IjuKqMe3aX IoS/j6ePVc21DDZe4DoA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkO44-00ArA0-J5; Fri, 29 Apr 2022 10:41:32 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkO41-00Ar8d-Hk for linux-riscv@lists.infradead.org; Fri, 29 Apr 2022 10:41:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651228889; x=1682764889; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=hb7qYyX9lqSS5ehCqpe6Z0ZB3U0YtPIUC2+n1GdDKfM=; b=Lx9rL5bxUI3aBgw73kW7ioYwoRAhCZsztpOE7wZZp2MPQ5UM8YWJU3m3 8dmTOAehX4bvzqDVdoL/ViSstH35a0N5zdftInOAI4iIL0bjHyuRuy1pJ mJK4vSxwz5v2YR0OQ/ci+9myz7mUGTayi969OOl75TGvBV/BRWHBYKSr1 gp8L5IYvQt05EnLdDcwm6zZOFsD7cJ49BMxH7X7ZmS8TUfWQTuMl/HnCT p7QZNinmgE2xZcsMPOqwtCvG71O9DSTeTLyhXvmgQqKmNBYeG5qJTgGwx bncdzYlaSdxOvCw/QHP3p2uheWVKglP2fmczVqxjfgmI77S6oy8vL6xq2 g==; X-IronPort-AV: E=Sophos;i="5.91,298,1647327600"; d="scan'208";a="94031874" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Apr 2022 03:41:26 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 29 Apr 2022 03:41:26 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 29 Apr 2022 03:41:23 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Daire McNamara , Cyril Jean , , , , "Arnd Bergmann" Subject: [PATCH v1 0/8] PolarFire SoC dt for 5.19 Date: Fri, 29 Apr 2022 11:40:33 +0100 Message-ID: <20220429104040.197161-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220429_034129_681012_B682D54B X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hey all, Got a few PolarFire SoC device tree related changes here for 5.19. Firstly, patches 1 & 2 of this series supersede [0] & are unchanged compared to that submission, figured it would just be easier to keep all the changes in one series. As discussed on irc, patch 3 removes the duplicated "microchip" from the device tree files so that they follow a soc-board.dts & a soc{,-fabric}.dtsi format. Patch 5 makes the fabric dtsi board specific by renaming the file to mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than mpfs.dtsi. Additionally this will allow other boards to define their own reference fabric design. A revision specific compatible, added in patch 4, is added to the dt also. The remainder of the series adds a bare minimum devicetree for the Sundance Polarberry. Thanks, Conor. [0] - https://lore.kernel.org/linux-riscv/20220425104521.132538-1-conor.dooley@microchip.com/ Conor Dooley (8): riscv: dts: microchip: remove icicle memory clocks riscv: dts: microchip: move sysctrlr out of soc bus riscv: dts: microchip: remove soc vendor from filenames dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: make the fabric dtsi board specific dt-bindings: vendor-prefixes: add Sundance DSP dt-bindings: riscv: microchip: add polarberry compatible string riscv: dts: microchip: add the sundance polarberry .../devicetree/bindings/riscv/microchip.yaml | 12 ++- .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/riscv/boot/dts/microchip/Makefile | 3 +- ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 + ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 5 +- .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ .../{microchip-mpfs.dtsi => mpfs.dtsi} | 11 +-- 8 files changed, 132 insertions(+), 14 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (93%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%) base-commit: a91b05f6b928e8fab750fc953d7df0aa6dc43547