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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:10 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v4 0/8] PolarFire SoC dt for 5.19 Date: Wed, 4 May 2022 21:30:44 +0100 Message-Id: <20220504203051.1210355-1-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_133513_708359_3C8DCCAC X-CRM114-Status: GOOD ( 13.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hey all, Got a few PolarFire SoC device tree related changes here for 5.19. Firstly, patches 1 & 2 of this series supersede [0] & are unchanged compared to that submission, figured it would just be easier to keep all the changes in one series. As discussed on irc, patch 3 removes the duplicated "microchip" from the device tree files so that they follow a soc-board.dts & a soc{,-fabric}.dtsi format. Patch 5 makes the fabric dtsi board specific by renaming the file to mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than mpfs.dtsi. Additionally this will allow other boards to define their own reference fabric design. A revision specific compatible, added in patch 4, is added to the dt also. The remainder of the series adds a bare minimum devicetree for the Sundance Polarberry. Thanks, Conor. Changes since v3: - remove an extra line of wshitespace added to dt-binding - remove unneeded "okay" status & sort status to node end - sort polarberry dts entries in ~alphabetical order - add a comment explaining why the second mac (mac0) is disabled on polarberry Changes since v2: - make ,icicle-reference compatible with ,mpfs & put it inside the enum Changes since v1: - fixed whitespace problems in the polarberry dts - disabled mac0 for the polarberry as its port is on the optional carrier board Conor Dooley (8): riscv: dts: microchip: remove icicle memory clocks riscv: dts: microchip: move sysctrlr out of soc bus riscv: dts: microchip: remove soc vendor from filenames dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: make the fabric dtsi board specific dt-bindings: vendor-prefixes: add Sundance DSP dt-bindings: riscv: microchip: add polarberry compatible string riscv: dts: microchip: add the sundance polarberry .../devicetree/bindings/riscv/microchip.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/riscv/boot/dts/microchip/Makefile | 3 +- ...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 + ...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 5 +- .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++ .../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++ .../{microchip-mpfs.dtsi => mpfs.dtsi} | 11 +-- 8 files changed, 128 insertions(+), 10 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%) base-commit: b6b2648911bbc13c59def22fd7b4b7c511a4eb92