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([171.76.104.191]) by smtp.gmail.com with ESMTPSA id i19-20020a056a00225300b00522c365225csm1427273pfu.3.2022.06.15.03.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 03:40:45 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Alistair Francis , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 0/3] Improve instruction and CSR emulation in KVM RISC-V Date: Wed, 15 Jun 2022 16:10:22 +0530 Message-Id: <20220615104025.941382-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220615_034049_765022_F620C1F3 X-CRM114-Status: UNSURE ( 7.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, the instruction emulation for MMIO traps and Virtual instruction traps co-exist with general VCPU exit handling. The instruction and CSR emulation will grow with upcoming SBI PMU, AIA, and Nested virtualization in KVM RISC-V. In addition, we also need a mechanism to allow user-space emulate certain CSRs under certain situation (example, host has AIA support but user-space does not wants to use in-kernel AIA IMSIC and APLIC support). This series improves instruction and CSR emulation in KVM RISC-V to make it extensible based on above. These patches can also be found in riscv_kvm_csr_v2 branch at: https://github.com/avpatel/linux.git Changes since v1: - Added a switch-case in PATCH3 to process MMIO, CSR, and SBI returned from user-space - Removed hard-coding in PATCH3 for determining type of CSR instruction Anup Patel (3): RISC-V: KVM: Factor-out instruction emulation into separate sources RISC-V: KVM: Add extensible system instruction emulation framework RISC-V: KVM: Add extensible CSR emulation framework arch/riscv/include/asm/kvm_host.h | 16 +- arch/riscv/include/asm/kvm_vcpu_insn.h | 48 ++ arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 34 +- arch/riscv/kvm/vcpu_exit.c | 490 +---------------- arch/riscv/kvm/{vcpu_exit.c => vcpu_insn.c} | 563 +++++++++++--------- include/uapi/linux/kvm.h | 8 + 7 files changed, 392 insertions(+), 768 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_insn.h copy arch/riscv/kvm/{vcpu_exit.c => vcpu_insn.c} (63%)