From patchwork Tue Jun 21 14:49:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 12889361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3173C433EF for ; Tue, 21 Jun 2022 14:50:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=E+ivA8b+9C09pbSv1O8SYmoB0x9q8t9d1gp/IwwpsKM=; b=ZHMS7D19Zwa9Sh scaDh2SZLwya9DaHey7SDH/aYq8kTuhQ7iBt7TTZq2hoBqptroLpu4DxXAUvZMrvdOFTwqxsG9pZr 3a08iOuNhtDIgZwm2PsmG/5FCR4AdvhcL/Fzt8vqLg00L/9eZ/5s15O57/jG+jR+BCZ8qWHBNUSiJ X0ZnAyD61kSEZ0e03FIp3BGXyBwTcQd/aat6xEBWaJh6l0qhyI4l2UPHi7PAl/wvUSFcTYEQKttDK MSyCUxo1Qt90i2ROrpAHG3nflr9EuaPvmoPbkPGC2gzCIHaO3qe0OcPfyVeFPGEGbj9DwQ2f5TNAS exDpV3ewPtRofh+DtxQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3fCR-005yV2-EO; Tue, 21 Jun 2022 14:49:51 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3fCN-005yTN-Ni for linux-riscv@lists.infradead.org; Tue, 21 Jun 2022 14:49:49 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C79AAB8197E; Tue, 21 Jun 2022 14:49:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71C0EC3411C; Tue, 21 Jun 2022 14:49:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655822983; bh=SZKgLW9pCUpPaA4Q2joB2cVjf3OSIICpzQIzPOyXTmo=; h=From:To:Cc:Subject:Date:From; b=q3170b0IF27mRdU22SwhXmvvuiW+lv6RfPUKC1/YwQ4Ho7JMBxwbRmQuZYUrsMHPt PYt/B2QlsCF3wEgBFDFj4GFRalU92JO1gDLagjBG98kJMgHSCHBzAfIZjNYf1GpNuO xfyyfhOrjq1Jn32cEfJHzhiJiWXSuKxp767ldZNTkL8RRWE/DhsjZq8qEphgzxXKb0 oCK9qancnHuOBA2xgGxwj/ltUMXLIrGDl5qyhtZ2EkvZH6m6IfhR3z1HSC5NTQd1h3 mBywDwuXt9j14wU1huTls2Bq9UYbxTvVyGwQ604q+hEsZvNvtpYbO4yE4V0oqFO7cl NE2N6pqaMUADw== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, peterz@infradead.org, longman@redhat.com, boqun.feng@gmail.com, Conor.Dooley@microchip.com, chenhuacai@loongson.cn, kernel@xen0n.name, r@hev.cc, shorne@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren Subject: [PATCH V6 0/2] riscv: Support qspinlock with generic headers Date: Tue, 21 Jun 2022 10:49:18 -0400 Message-Id: <20220621144920.2945595-1-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_074948_068312_13E479A2 X-CRM114-Status: GOOD ( 13.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9 ("asm-generic: qspinlock: Indicate the use of mixed-size atomics"). RISC-V LR/SC pairs could provide a strong/weak forward guarantee that depends on micro-architecture. And RISC-V ISA spec has given out several limitations to let hardware support strict forward guarantee (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional Instructions): We restricted the length of LR/SC loops to fit within 64 contiguous instruction bytes in the base ISA to avoid undue restrictions on instruction cache and TLB size and associativity. Similarly, we disallowed other loads and stores within the loops to avoid restrictions on data-cache associativity in simple implementations that track the reservation within a private cache. The restrictions on branches and jumps limit the time that can be spent in the sequence. Floating-point operations and integer multiply/divide were disallowed to simplify the operating system’s emulation of these instructions on implementations lacking appropriate hardware support. Software is not forbidden from using unconstrained LR/SC sequences, but portable software must detect the case that the sequence repeatedly fails, then fall back to an alternate code sequence that does not rely on an unconstrained LR/SC sequence. Implementations are permitted to unconditionally fail any unconstrained LR/SC sequence. eg: Some riscv hardware such as BOOMv3 & XiangShan could provide strict & strong forward guarantee (The cache line would be kept in an exclusive state for Backoff cycles, and only this core's interrupt could break the LR/SC pair). Qemu riscv give a weak forward guarantee by wrong implementation currently [1]. The first version of patch was made in 2019.1 [2]. [1] https://github.com/qemu/qemu/blob/master/target/riscv/insn_trans/trans_rva.c.inc [2] https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r Change V6: - Fixup Clang compile problem Reported-by: kernel test robot - Cleanup asm-generic/spinlock.h - Remove changelog in patch main comment part, suggested by Conor.Dooley@microchip.com - Remove "default y if NUMA" in Kconfig Change V5: - Update comment with RISC-V forward guarantee feature. - Back to V3 direction and optimize asm code. Change V4: - Remove custom sub-word xchg implementation - Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock Change V3: - Coding convention by Peter Zijlstra's advices Change V2: - Coding convention in cmpxchg.h - Re-implement short xchg - Remove char & cmpxchg implementations Guo Ren (2): asm-generic: spinlock: Move qspinlock & ticket-lock into generic spinlock.h riscv: Add qspinlock support arch/riscv/Kconfig | 8 +++ arch/riscv/include/asm/Kbuild | 2 + arch/riscv/include/asm/cmpxchg.h | 17 +++++ include/asm-generic/spinlock.h | 90 ++------------------------ include/asm-generic/spinlock_types.h | 14 ++-- include/asm-generic/tspinlock.h | 92 +++++++++++++++++++++++++++ include/asm-generic/tspinlock_types.h | 17 +++++ 7 files changed, 146 insertions(+), 94 deletions(-) create mode 100644 include/asm-generic/tspinlock.h create mode 100644 include/asm-generic/tspinlock_types.h