From patchwork Mon Aug 15 13:22:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 12943593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA0D3C25B0E for ; Mon, 15 Aug 2022 13:29:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=/F8Leo7YDTc9XeQDSqPgk+qRpcwhnod1I3KdFb+ig9k=; b=aj5Y77O8/n+JtC DCRnon4LszlgWgvQL+yT24iALzpWTSh09/99Q6rQ2R8jPTg3cb5ZVBgzXkXDOaVyKDks82M16ndEm wBICqKdnciCyaGnSQTikA24wumJCvhPvFPyOOxXPfLc7hIKDS5015chpmtNpm2zoiOLlUl8DHRgdv WBM+CPlQ9lCfmZBtUuBRBQEXuz76hW3iFkZNlJuP1Qolin77D8+1RL/ibM85asD0iDzul/u1FOW16 2b/3qLdcB0j4hzfoPbY7GSRfCFh6eZnaWNCuJCjkcd9foW309gdaYdu0FINDChFUj2lqHdpOjDL++ fTTQZASM+/BfpZFlaNnw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNa9b-00GoVW-8m; Mon, 15 Aug 2022 13:29:15 +0000 Received: from forward105j.mail.yandex.net ([2a02:6b8:0:801:2::108]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNa3j-00Gk3s-O8 for linux-riscv@lists.infradead.org; Mon, 15 Aug 2022 13:23:15 +0000 Received: from iva1-dcde80888020.qloud-c.yandex.net (iva1-dcde80888020.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:7695:0:640:dcde:8088]) by forward105j.mail.yandex.net (Yandex) with ESMTP id DE9444EC8F72; Mon, 15 Aug 2022 16:22:54 +0300 (MSK) Received: by iva1-dcde80888020.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id BL0XdiM9S6-Mpi4xxLF; Mon, 15 Aug 2022 16:22:53 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1660569773; bh=nIVrrngh255xQlyPNLMT0qsuvgBZKO7rCfvaAHKtXx0=; h=Message-Id:Date:Cc:Subject:To:From; b=c4RdYZOP23tRHPJkalribKDnE7knA0o8myJU9Heo9WbK55Q0IiPlvF4QVPkXlYTi+ AOo/KMX5aOKQxXUn8hztaBWOP6bTGhW1eMn3+6dmJnM0l3ZMYDac1fQKGSSHpZp0xl cNyIsiBpsRdkojnXyj7yxukIpsGu0hGkU0bIjmYE= Authentication-Results: iva1-dcde80888020.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Cc: linux@yadro.com, Anup Patel , Arnaldo Carvalho de Melo , Nikita Shubin , Albert Ou , Alexander Shishkin , Ingo Molnar , Jiri Olsa , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Namhyung Kim , Palmer Dabbelt , Paul Walmsley , Peter Zijlstra Subject: [PATCH v6 0/3] RISC-V: Create unique identification for SoC PMU Date: Mon, 15 Aug 2022 16:22:37 +0300 Message-Id: <20220815132251.25702-1-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220815_062312_277478_8DE1E078 X-CRM114-Status: UNSURE ( 9.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Nikita Shubin This series aims to provide matching vendor SoC with corresponded JSON bindings. The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example for Sifive Unmatched the corresponding string will be: 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core Where MIMPID can vary as all impl supported the same number of events, this might not be true for all future SoC however. Also added SBI firmware events pretty names, as any firmware that supports SBI PMU should also support firmare events [1]. Series depends on patch by Anup Patel, exposing mvendor, marchid and mimpid to "/proc/cpuinfo" [2]. [1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://lkml.org/lkml/2022/7/27/23 Link to previous version: https://patchwork.kernel.org/project/linux-riscv/list/?series=653649 See original cover letter by João Mário Domingos: https://patchwork.kernel.org/project/linux-riscv/cover/20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt/ Tested with the following OpenSBI device tree bindings: ``` pmu { compatible = "riscv,pmu"; riscv,event-to-mhpmcounters = <0x03 0x06 0x18 0x10001 0x10002 0x18 0x10009 0x10009 0x18 0x10011 0x10011 0x18 0x10019 0x10019 0x18 0x10021 0x10021 0x18>; riscv,event-to-mhpmevent = <0x03 0x00000000 0x1801 0x04 0x00000000 0x0302 0x05 0x00000000 0x4000 0x06 0x00000000 0x6001 0x10001 0x00000000 0x0202 0x10002 0x00000000 0x0402 0x10009 0x00000000 0x0102 0x10011 0x00000000 0x2002 0x10019 0x00000000 0x1002 0x10021 0x00000000 0x0802>; riscv,raw-event-to-mhpmcounters = <0x00000000 0x03ffff00 0x0 0x0 0x18 0x00000000 0x0007ff01 0x0 0x1 0x18 0x00000000 0x00003f02 0x0 0x2 0x18>; }; ``` Acked-by: Palmer Dabbelt --- v5->v6: Will Deacon: - dropped first patch from v5 series it has been merged into master Mayuresh Chitale: - fixed FW_SFENCE_VMA_SENT event code - added Tested-by tags --- Nikita Shubin (3): perf arch events: riscv sbi firmware std event files perf vendor events riscv: add Sifive U74 JSON file RISC-V: Added Syntacore SCR7 PMU events tools/perf/pmu-events/arch/riscv/mapfile.csv | 18 +++ .../arch/riscv/riscv-sbi-firmware.json | 134 ++++++++++++++++++ .../arch/riscv/sifive/u74/firmware.json | 68 +++++++++ .../arch/riscv/sifive/u74/instructions.json | 92 ++++++++++++ .../arch/riscv/sifive/u74/memory.json | 32 +++++ .../arch/riscv/sifive/u74/microarch.json | 57 ++++++++ .../arch/riscv/syntacore/scr7/L1D_cache.json | 102 +++++++++++++ .../arch/riscv/syntacore/scr7/L1I_cache.json | 67 +++++++++ .../arch/riscv/syntacore/scr7/exceptions.json | 67 +++++++++ .../arch/riscv/syntacore/scr7/execution.json | 97 +++++++++++++ .../arch/riscv/syntacore/scr7/firmware.json | 68 +++++++++ .../arch/riscv/syntacore/scr7/general.json | 47 ++++++ .../arch/riscv/syntacore/scr7/interrupts.json | 32 +++++ .../arch/riscv/syntacore/scr7/prediction.json | 52 +++++++ 14 files changed, 933 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/L1D_cache.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/L1I_cache.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/exceptions.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/execution.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/general.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/interrupts.json create mode 100644 tools/perf/pmu-events/arch/riscv/syntacore/scr7/prediction.json