From patchwork Fri Aug 19 12:22:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B82D3C32772 for ; Fri, 19 Aug 2022 12:28:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=9NDKvVZ+ct/dlrkj6AlQxEiiQu/a/587ncSjDuLULD4=; b=l4llpnb+i/YfXp aXG2ZYuvD7XSd6WYCi+LabvtXuhZyalswBpQhPEiRKXQGhYwnREVKX60ioobiU/mNaSitYw5fPM7K UXRvkUb8kiqIJx9t1kVf9KcG3OnsqFv0imw5/DF7J74NMsA9DMkWUhApk69Y9V2YouLaKuKS2bUxu 39ZZeuHKg8UTYHjlGnlLGxtqxms2VxxrTKAtjLb1Siw6lFN86eAsIIMA0sd9BDR3KA2PljkkJUIO7 XNUdTb0IpiBE1c0JjqPl8dO/Pn5b/U73JLUdVpCM3z9kJHGzC0Ed47n61QXkEUYckqw8JAeT4qAm4 KJIQRV/jKCZ+VF9qNcBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oP16q-007rr0-R6; Fri, 19 Aug 2022 12:28:20 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oP16k-007rOL-Ig for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 12:28:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660912094; x=1692448094; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=OuppHraavVdcPp0ARLA7zsvgdMH5yWNmIVqS5fqgRKI=; b=Rk6eLgllFy0AE9L7imfGQ3ZYWca5fmCv9tjs0/cnOxUGe+8ZtzKqB+2F R6l9fa77kFH+l+jxGFCwSyTWazXEigujZqlYT3KkA/DbBO2JwHgjDGAGG l08KQwvUavZzPDI6vdqTDyCuCT0FdAxZvRtUdfV+Ezv3869zbjJjw+zs0 KsJFYWtnj6+U95F1/lu1DBa2i462mqszG5z5towbTlHtOVWVNIW2MdVrf 6L3mxSqj+9oWJ2JWvYtTAE409K091bRk9109blZ+TCyX92stWCV+CEFgG W+yBAH9CkGGkM5VgRAizdvky9IgM66NvRzB09k4vH/IYoDAlbwF5H7jlw Q==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="173199554" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 05:28:07 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 05:28:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 05:27:59 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support Date: Fri, 19 Aug 2022 13:22:54 +0100 Message-ID: <20220819122259.183600-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_052814_731577_8B2FDBE7 X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hey all, PolarFire SoC has 4 clock source blocks, each with 2 PLLs and 2 DLLs, in the corners of the FPGA fabric. Add bindings, a driver supporting the PLLs and the requisite changes to the devicetrees for PolarFire SoC based boards. These clocks were already in use, but which clock specifically was chosen was decided by the synthesis tool. In our end-of-September release of our FPGA reference design, constraints will be added to force the synthesis tool to pick the "north west" CCC, making it possible to read the configuration from the CCC's registers. I am mainly looking for feedback on the dt-bindings on this version, so that if something dt-abi related needs to change it can be done in advance. There are no maintainers changes in this series, but they are required due to the binding rename. I am waiting for some changes queued in the soc tree before rebasing on a later -rc before including that patch. Thanks, Conor. Conor Dooley (6): dt-bindings: clk: rename mpfs-clkcfg binding dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: add PolarFire SoC fabric clock ids clk: microchip: add PolarFire SoC fabric clock support dt-bindings: riscv: microchip: document icicle reference design riscv: dts: microchip: add the mpfs' fabric clock control .../bindings/clock/microchip,mpfs-ccc.yaml | 80 +++++ ...p,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +- .../devicetree/bindings/riscv/microchip.yaml | 1 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +- .../boot/dts/microchip/mpfs-icicle-kit.dts | 4 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +- drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs-ccc.c | 294 ++++++++++++++++++ .../dt-bindings/clock/microchip,mpfs-clock.h | 23 ++ 10 files changed, 458 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%) create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868